I am experiencing failures of the LSE oscillator on STM32F427VIT6 during thermal cycling.

[BRieh.1]

I have an ESC ECS-.327-CDX-1082 32.768KHz crystal on the LSE of an STM32F427.

I have read and followed AN2867.

All of the boards produced so far have had the oscillator come up initially.

All of the boards subjected to thermal cycling (-20°C to +70°C) have failed. (two)

In each case, the voltage on the pins (GPIO PC14 & PC15) measures 0 volts.

I expect somewhere about 0.3V.

I just replaced the MCU on one of the boards and now the oscillator works again.

Any thoughts?

[Bob S]

I don't recall - that was a while ago. But I wouldn't be surprised if once the oscillator fails, it stays "failed" until power is cycled.

[BRieh.1]

Cycling power has never corrected this issue.

Replacing the microcontroller has.

[BRieh.1]

That's not quite true:

I have a 0.22F Kemet EDLC Supercap holding up the Vbatt pin on the MCU.

Discharging the supercap does indeed result in LSE start up.

Thanks.

[Tesla DeLorean]

Perhaps there is some RTC side issue. Dump the register content for RTC / BKP / PWR

I've flagged the thread for review, hopeful someone from ST will dig more deeply.

[BRieh.1]

With the LSE up and running, I dripped some IPA over the circuit and indeed, the LSE stopped.

When the IPA evaporated, the LSE begins to run again.

[waclawek.jan]

> I have a 0.22F Kemet EDLC Supercap holding up the Vbatt pin on the MCU.

Oh. New info.

Does "thermal cycling" happen under VDD power, or only under VBATT supplied by the supercap? In the latter case, doesn't the supercap discharge significantly during the test? If so, can't the observed behaviour be consequence of VBAT-domain brownout?

Try using a primary Li cell (e.g. 2032) instead of the supercap.

JW

[BRieh.1]

Thermal cycle consists of 1.5 hours of Vdd power from ambient to +70°C then to 0°C when Vdd power is removed and the LSE +RTC are powered by Vbatt via the supercap for 1.5 hours. After the 1.5 hours, Vdd power is reapplied and LSE fails to start. Likely, the Vbatt level is such that the LSE is unhappy.

Today, I performed the same profile but instead of removing all power, input power was continuously applied (suppling charging voltage to the supercap) and using the Keyswitch input all remaining circuity was powered down. At the end of the 1.5 hours at 0°C, the LSE failed to start. There was 2.2V to Vbatt at the time.

I have been unable to duplicate these symptons on the bench.

Much to my chagrin, Coin cells are not an option for this device.

[waclawek.jan]

2.2V VBAT should be sufficient plenty, so this might indeed be temperature-related.

OTOH, the supercap is relatively high capacitance. Isn't 2.2V unexpectedly low voltage after 1.5h?

Others may have mentioned above: it would be enlightening to hot-connect a debugger and read out the backup-domain-related registers' content a the moment of failure.

The crystal itself as well as the capacitors (negligibly perhaps for C0G) and the silicon of the oscillator's amplifier are all both temperature and voltage dependent. And, if condensation is a possibility, as Bob said above, that's a concern too. We're talking ultralow consumption circuit here. Try conformal coating.

JW

[BRieh.1]

The solution is to do a backup domain reset. There appears to be a finite amount of time between the backup domain reset and the re-enabling of the LSE oscillator. We can now sucessfully recover from this event. Thanks to all of you who have contributed.

[BRieh.1]

Also, the voltage provided by the supercap never dropped below 2.1 volts.

[waclawek.jan]

Thanks for coming back with the solution.

> There appears to be a finite amount of time between the backup domain reset and the re-enabling of the LSE oscillator.

Can you please be a little bit more specific, i.e. how much?

Thanks,

JW

PS. Please select your post as Best so that the thread is marked as solved.