Hi,The RM0091 rev 9 has some contradictions and typos in the ADC chapter.on page 234, 13.4.4 says that the registers IER, CFGRi, SMPR, TR, CHSELR and CCR must be configured only after ADEN has been set (and presumably that ADRDY is also set).However in section 13.5.2, it is said that the RES bits in CFGR1 must only be changed when ADEN = 0.So which one of the above should I follow ?on page 252, for calculating the Vdda value, a value of .3V is mentionned twice (I presume 3.3V, as written in the next formula).Best regards.

K

Kraal

Senior III

Question

RM0091 - ADC chapter not very clear

Forum|Forum|5 years ago
April 6, 2021
7 replies
1473 views

Hi,

The RM0091 rev 9 has some contradictions and typos in the ADC chapter.

on page 234, 13.4.4 says that the registers IER, CFGRi, SMPR, TR, CHSELR and CCR must be configured only after ADEN has been set (and presumably that ADRDY is also set).
However in section 13.5.2, it is said that the RES bits in CFGR1 must only be changed when ADEN = 0.
So which one of the above should I follow ?
on page 252, for calculating the Vdda value, a value of .3V is mentionned twice (I presume 3.3V, as written in the next formula).

Best regards.

This topic has been closed for replies.

waclawek.jan

Super User

https://community.st.com/s/question/0D50X00009XkaB8SAJ/rm0367-stm32l0x3-discrepancies #7

I wouldn't be surprised if any of the other issues mentioned there would be pertinent to the 'F0 ADC, or for that matter, for ADC of the same version.

https://community.st.com/s/ideazone#0873W000000KykTQAS

JW

I

Imen.D

ST Technical Moderator

Hello @Kraal , @Community member ,

Thanks for pointing out these typos.

I am checking this and I will raise your feedback internally for clarification and correction in the impacted reference manuals.

Thanks

Imen

In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question. Thanks

waclawek.jan

Super User

Thanks, Imen.

Jan

waclawek.jan

Super User

The formulation of said "warning" in RM0367 has been changed to:

For all the other control bits in the ADC_IER, ADC_CFGRi, ADC_SMPR, ADC_TR,

ADC_CHSELR and ADC_CCR registers, refer to the description of the corresponding

control bit in Section 14.12: ADC registers.

and indeed, most if not all control bits/bitfields in the related registers now have a note, saying when the given bit/bitfield must not be changed; most of them say

Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing).

Except of the "logical" ones (ADSTART, ADDIS), I believe that only ADC_CALFACT.CALFACT requires ADEN=1.

The 'F0 ADC may/is different. e.g. https://community.st.com/s/question/0D53W00000gh4S1SAI/causes-for-adc-calibration-not-finishing

RM00901 for the 'F0 hasn't been updated from v9 for ages (RM0360 probably too). I believe there are tons of changes pending.

JW

K

KraalAuthor

Senior III

@Community member correct, after reading again the registers section of the ADC chapter, it is almost always said that the modification of bit nn must be done when ADSTART = 0 (so no ongoing conversion). Obviously ADSTART = 1 is only possible when the ADC has been enabled before.

So with the exception of the RES bits, I believe that ADEN must be set before configuring the ADC.

As said before, I never had any issue doing otherwise, but you never know what could go wrong with the details.

@Imen DAHMEN I would suggest an additional snippet at the end of the RM with a configuration of the ADC so that it should be impossible to misunderstood.

Best regards,

Carl

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