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Hi,    I bought VIPER06LN from mouser. Please help me check the COD. The Chinese custom need this information.   Thank you

I am using STM32C071FBP6N MCU TSSOP 20 pin package for one of our project.I am observing Pin_20 is muxed with lot of other pins like PB3/PB4/PB5/PB6. if i select PB3 as GPIO_Output using STM32CubeMx and generated a code. If i try to toggle the pin but its not working at all, none of the peripheral on that pin for PB3 is working. But if i select PB6 as GPIO_Output i can able to toggle or modify.This issue is not only with Pin_20, same with Pin_1 also which shares with PB7/PB8, only PB7 is working.I have tried with multiple chips what could be wrong in this scenario??

I am generating a PWM signal using timer1 register and use it in Center aligned mode. I want to to know if i can modify the timer counter register TIMx_CNT register with some "x" value in the timer interrupt instead of resetting it to 0. 

Hello I am trying to implement I²C slave on a STM32U385RGTxQ in non-blocking mode, on I2C2.To match I²C standard I tried to use the Address macthed interruption but the interruption is never trigged. I used the function HAL_I2C_EnableListen_IT(&hi2c2) to enabled it; My issue is, I don't reach neither the I2C2_EV_IRQHandler(void), the I2C2_ER_IRQHandler(void) or the HAL_I2C_AddrCallback() when sending the slave address.  Please found attached my project. And bellow some pictures of my I2C2 init, an oscilloscope capture and my I2C2 register when I am in debugger :         Best Regards Thibaud HABRAND      

Hi,I'm designing a board with STM32MP153FAD and have a question about DDR layout reference.Which reference should I follow for the DRAM section?Eval kit MB1272C_03 layoutST's published reference DDR layout.Questions:Which is the recommended reference for custom board design?Is there a design guide specifically for STM32MP153 DDR layout and routing guidelines?Is there a document listing pin delays for the FAD series SoCs? This would be helpful for length matching calculations.Best regards,Batuhan

Hello,I've just received my fresh new SMT32H747I-DISCO dev board and I wanted to try some samples.I have some experience deveolping on embedded Liuxes, but this is my second MCU (the first one was a Raspberry PICO, don't know if this counts). I am using a MacBookPro with Apple silicon (M3) and MacOS 14.4What I have done:read the specs, configured the board to get power and STLink from CN2 (as is by factory)installed every tool available:STM32CubeProgrammerSTM32CubeIDE (which also installed a SMTLink server nstall ,st-stlink-server.2.1.1-2, installed successfully ) even STM32CubeMXconnected the board to a USB-C port on my Mac via a USB-C to USB-B mini cable2 times out of three the main led (LD10?) starts red, then flashes red/green then stays green. The other times the board LED stays red. In either case, nothing on the LCD display. to me the board seems waiting.On the former occurrences, MacOS then asks me for permission to connectbut that's it. I wanted to install the Tutti Fruit

I am not able to erase a section of internal flash of the NUCLEO-H633RE.Using the debugger I see the Flash is all 0x00 before I try to erase.  I verify that Flash is not locked i.e.if (*FLASH_NSCR && LOCK) { *FLASH_NSKEYR = 0x45670123; *FLASH_NSKEYR = 0xcdef89ab; }then I try to erase a section of Flash i.e./* ************************************************************************* */ /* */ /* EraseFla - Erases 8K page of Flash, Waits for Flash not busy. */ /* Inputs: uint32_t page holds the page to erase. */ /* Outputs: None */ /* */ /* ************************************************************************* */ void EraseFla(int EraPage) { while (*FLASH_NSCR && BSY){}; n = *FLASH_PRIVCFGR; // just testing n = EraPage >> 7; if (n && 0x0800) { n &= 0x07C0; n |= 0x80000004;} // BKSEL and SER else { n &= 0x07C0; n |= 0x00000004;} *FLASH_NSCR |= n; *FLASH_NSCR |= STRT; while (*FLASH_NSCR && BSY){}; }  With the debugg

English language:STM32H7 Ethernet + DMA + Cache Explained + LwIP (EN) One of the most common sources of confusion when working with STM32H7 microcontrollers and Ethernet (via LwIP + HAL ETH) is data cache (D-Cache) behavior.When using DMA (like Ethernet MAC DMA), if D-Cache is enabled (which it is by default in STM32H7 projects), you must manage cache coherency manually. Otherwise, the DMA peripheral and the CPU will not agree on what data is in RAM.I encountered this exact issue myself and spent significant time identifying the root cause. Since many others using STM32H7 are likely to face this same problem, I'm sharing this explanation to help save your time and effort.Problem:If you fill a pbuf->payload buffer with data and send it using HAL_ETH_Transmit() without cleaning the D-Cache, the CPU will still be holding the most recent data in its cache, but the DMA will read stale or uninitialized data from RAM.Result: corrupted Ethernet frames, broken ping replies, UDP iss

Hey!Does anyone recognice this part?It`s marked with C306 (ST- Sign) FRO169.It looks like a transistor or diode in SOT-229 package.Thanks!Frank

Hi all, Thank you for looking at my thread.I have started a proof of concept project that runs ThreadX and TouchGFX on a custom QSPI display on STM32F7. I noticed from the documentation at https://support.touchgfx.com/docs/development/touchgfx-hal-development/scenarios/scenarios-configure-rtos that the following warning is highlighted.Now indeed when I generate the code from CubeMX the MX_TouchGFX_Init is not getting called from anywhere, and in the documentation it suggests to call it from app_azure_rtos.c in the tx_application_define method.However in such method the main thread is already been initialized.If i replace App_ThreadX_Init with MX_TouchGFX_Ini, I am getting a TX_POOL_ERROR.What am I supposed to do to initialize TouchGFX?Thank you 

Hello,The latest version of STM32CubeMX no longer lists x-cube-spn5 as an available package.Could someone help me how to use a X-Nucleo-IHM05A1 expansion board with the latest tools please? 

Good morning everyone, I have this Mini STM32F103C8T6 CH340 board which supposedly has the original chip (photo), I configure it as suggested in a post I saw here but it gives an error (attachment).Does anyone have a solution?Edited to place Images in-line for easier viewing:  

Hi everyone,I'm experiencing a very specific bus/clock issue on a custom board using the STM32U5G9ZJ (and also tested on STM32U5F9ZJ).The Problem: My display (320x240, RGB565 via LTDC) only works if the HSPI1 peripheral is enabled in CubeMX. As soon as I disable HSPI1 (which I need to do to free the PH9 pin for power management reasons), the screen turns grey, even though the LTDC settings remain unchanged.Key Technical Details:Data Location: All assets (images/fonts) are stored in Internal Flash memory. The HSPI/OctoSPI bus is NOT used during the display process.Memory Status: In Debug mode, I can confirm via the Memory Browser that the Frame Buffer (located at 0x20025800) is correctly populated with pixel data.LTDC Behavior: Despite the RAM being correct, the LTDC fails to output data to the panel when HSPI1 is OFF.Configuration: Pixel Clock (PLL3R) is at 200MHz, GPIOs are "Very High Speed", and the Frame Buffer is placed to avoid conflicts with the RTOS (ThreadX) heap.The Mystery: W

Hello!I have implemented one of the key parts of a speech recognition system on the STM32N6 without using the cloud. I would like to describe my results in more detail, but it seems to me that the “New Message” section is not the right place for that. Could you please advise me where it would be better to share this? 

Hello,I want to know the DAC output buffer maximum safe output current before damaging the output buffer. I know that it's not possible to get the output swing mentioned in the datasheet under this condition.The datasheet maximum ratings doesn't state it for the DACs, and from the normal ratings only the current to keep the maximum output voltage around VREF+ can be calculated. So, either I wasn't able to locate the information in the datasheet (which is hopefully the case) or it isn't mentioned there at all.I'm using a STM32U083 device, datasheet https://www.st.com/resource/en/datasheet/stm32u083kc.pdfRegards

I created the project in TouchGFX 4.26.0 Designer, modified pins with CubeMX_17, and attempted to debug the project in STM32CubeIDE 2.1.1. The example I used was Flex Button Example.Kit is STM32U5G9J-DK2.When I attempt to set up a debug configuration in CubeIDE, I am unable to select a project. This project compiles and works when I flash it to my kit through TouchGFX. Could there something wrong with my project structure? Thank you. 

Hello, Using STM32F4 USB USB_OTG_HS, PCD_SPEED_FULL for USB Device CDC we are transmitting data to Host.After some minutes the transmission gets stuck. Although the TXFE IRQ is received, no XFRC IRQ happens and consequently TX state is not set back to 0. The DTXFSTS counter stays on 0x40 (empty is 0x80).The USB trace looks normal. When the problem occurs the peripheral answers all IN Transactions with a NAK.Why does the peripheral not transmit the data but does NAK instead?The problem is seen with different types of Hosts (PC or other embedded devices).Attached Log Output and Screenshot of the Trace.HAL 2.4.2 us used. The TxState fix was applied (Enable/Disable IRQ moved to USBD_CDC_TransmitPacket)Many thanks for any help.

For our product we use sliders to set parameters in our software. Some parameters effect the range of others at runtime. Sometimes the allowable range of the values is limited to a single value. In such a case min equals max. This leads to an assert error in the simulator and undocumented behavior on the target.We would like to see support for min=max. One way to implement it is to show the Indicator Image in the center (or left),  disable sliding, and set the value=min=max. This would simplify our firmware since we wouldn't need to handle it as a special case.I also added the tag bug-report since undefined behavior on the target is unacceptable.

Hi@all Curently i was using STM32F407VGTX but i found that there is no support of snmpv3 on this board so i decided to go for stm32H753ZI. Kindly please suggest that does this board supports snmpv3 or not and if not please suggest me the board that supports snmpv3 i want to deploy in my products 

Environment:Tool: STM32Cube.AI Studio (Windows Desktop)MCU: STM32N647 (Flashless)Board: Custom board (Non-ST DK/Nucleo)Issue: The Memory Pool option is locked to "Auto" and cannot be switched to "Manual" in the GUI. Since STM32N647 has no internal Flash, the default "Auto" mode triggers a Memory Overflow error as it attempts to place weights in non-existent Flash.Question: I have already prepared a custom mpool and Jason file. How can I explicitly point the Studio to use this JSON file via the GUI? I've checked the Wiki but couldn't find the specific input field...   

Hello, I am experiencing an I²C communication issue between my MPU6050 sensor and an STM32F429I-DISC1 board. The sensor is properly powered at 3.3 V, and I have already verified its operation with an ESP32 board (communication is successful). However, with the STM32, no communication is established. Actions performed: Configured I²C1 on the STM32 (tested in fast mode at 400 kHz and standard mode at 100 kHz) Verified the MPU6050 address (default 0x68, AD0 pin connected to GND) External pull-ups: tested with and without 4.7 kΩ resistors on SCL and SDA Checked physical connections (SCL to PB6, SDA to PB7 for I²C1 on the board) Configured the LCD screen Observed behavior: The I²C scan does not detect any address Blocking point: The same sensor, using the same basic I²C code, works perfectly on the ESP32. Therefore, the sensor is not the cause. The issue appears to be related to the I²C configuration on the STM32 or a hardware detail. Question: Has anyone encountered this behavior with

Hello,I currently need to transfer ADC data from a nucleo-n657x0Q to a PC. I've configured the stm32n6 using ST's example on GitHub, but I still don't know how to use the `ux_device_class_cdc_acm_write` function to transfer the data.Can anyone guide me on how to transfer data using this USB HS?

Hi,This is my first time using an STM32N6 without internal flash, and since I am right before handing over files for artwork, I would appreciate it if you could check if the power lines and XSPI memory connections are correct.I have searched around a lot, but since it is my first time, I feel a bit nervous, so please let me know if everything is correct.>I looked it up and found that to boot via Nor-Flash (quad), I need to connect XSPI1 to XSPIM_P2. Also, since I try to connect the 16-bit PRAM in DTR without DQS mode, I connected it as XSPI2->XSPIM_P1. Is this correct? I really need to BOOT via Nor-Flash and use PRAM after that. (swapped mode? in CubeMX)>This is the power line. It operates at 1.8V, and an STM employee told me to connect all CSI/USB lines to ground if I am not using CSI/USB. Is this the correct way like this all? I won't be able to fix it if the power section is wrong, so I would really appreciate it if you could let me know.  

When I clicked the "Access to MCU Selector" button, the interface did not respond. The pointer just kept rotating to indicate loading. However, when I clicked the "Access to Board Selector" button at this time, the selection interface could be opened.On the board selection interface, when I clicked the MCU/MPU Selector interface, it still showed the situation where the pointer was rotating and indicating a loading process, and I did not enter the MCU selection interface. 

Hello ST Community, I am currently evaluating an architecture based on STM32H7 series MCUs (STM32H743 / STM32H7A3) and would appreciate guidance on external memory scalability and best practices. Target Architecture Bootloader in internal Flash Main application stored and executed from external OctoSPI NOR Flash (XIP mode, memory-mapped at 0x90000000) External RAM for buffering (TCP/IP, DLMS stack, application data) Planned External Memory External NOR Flash via OctoSPI (large size, potentially >512 Mbit) External RAM target: ~256 MB (initial requirement) Key Questions 1. XIP Execution from OctoSPI NOR Is full application execution from OctoSPI NOR considered reliable for production systems? What are the recommended: MPU settings for external flash (cacheable, bufferable, execution attributes)? I-Cache / D-Cache configuration? Are there known limitations regarding branch-heavy code or interrupt latency when executing from external flash? 2. External SDRAM via FMC What is t