How to configure DMA correctly with D-Cache enabled on STM32H723?
Recently, I started using the ST67W6 Wi-Fi module on a custom PCB with an STM32H723VET MCU to implement the HTTP Server application provided by ST.
The application requires D-Cache to be enabled in order to operate correctly. However, as soon as I enable the D-Cache, my other peripherals that rely on DMA transfers, such as SDMMC and ADC, stop working correctly or fail completely. When I disable the D-Cache, all of these peripherals work normally again, but the HTTP Server application no longer functions, and I am unable to detect or connect to the Wi-Fi network.
From what I have studied, I suspect that the issue is related to cache coherency between the CPU and DMA peripherals. My understanding is that I may need to configure the MPU to place DMA buffers in a non-cacheable memory region, or otherwise separate the memory used by the Wi-Fi module from the memory used by other DMA peripherals.
However, I am still learning about MPU configuration, cache management, and memory mapping on STM32H7 devices, so I would greatly appreciate some guidance on the correct approach, because I am not confident at my understanding of it as of now.
Could someone please advise on the recommended MPU/cache configuration for an STM32H723 using the ST67W6 Wi-Fi module together with other DMA peripherals such as SDMMC and ADC?
Thank you in advance for any assistance, and if I am missing any crucial information that will be needed to help me out, please inform me.
