What exactly starts the clk during spi communications?
According to section 28.9.1 (of RM0091), the spi communications are enabled when register 6 is active (SPE set to 1). According to the rm0091 guide, once the spi communications are active, and register 14 is set to 0 (receive only mode) then the clk pin should start up. But when I pause the debugger at that stage, I can see both those pins be in the correct setting, but sometimes the clock is on and sometimes it is not on. So what exactly starts the clk during spi communications?
I dont know if it matters, but I am connected in half duplex master mode to an spi compatible chip (ssc). I am using an stm32f042k6t6 chip on a nucleo board.
