HardFault on attempt to perform unaligned access on ldr.w and blx.w instructions

> Can I tell the compiler to not create unaligned addresses?

Cortex-M-specific toolchains tend to come with settings which do generate aligned addresses. Howevr, you can't generally prevent the *user* to generate unaligned address accesses. simply by some pointer juggling.

Debug the hardfault in the usual way (walk back manually through mixed-C-disasm while observing registers' content) to find out exactly what source lines caused the unaligned access. Post it here for further discussion.

JW

Hi, I am getting the same hard fault while using lwIP and Ethernet with STM32F746G DISC board.

And @Community member​ 's answer still applies. See what code is that the given PC address and see if you can determine why it generated the fault.

Generally the F7 supports unaligned access except for LDM, STM, LDRD and STRD instructions. There is a bit in the CCR register that can enable unaligned access faults when they otherwise might be allowed. See PM0253.

Hi, I attached my project for review I am just trying to ping my board but I don't see any response. I set up the Rx,/Tx_Descrip and Rx/Tx_Buf in SRAM1 region. Above that I give access to lwIP_Heap Memory. Please check and make it functional. Code is running but no response from board. II am using STMCubeIDE 1.6.1 with CubeMX 1.6.2

I need to parse incoming packets with structure like

{
uint8_t packet_id;
uint16_t packet_CRC;
uing8_t var1;
double var2;
...
}

 For M7 core (STM32H755) CubeIDE make code that generates "unaligned access" hard fault on simple access of unaligned variables like  

IncomePacked.packet_CRC = calculated_CRC;
double MyVar = IncomePacked.var2

, etc.

I have need to add "-mno-unaligned-access" compiler option to rid that faults.

Strange, but M4 core works OK with the same code without additional options.