Count external pulses

> But triggering capture by a second timer and generating interrupt on capture did not work

Read out and check/post content of both timers' registers.

JW

For my tests I am using stm32l412kb because I have an eval board with it here. But I want to use stm32f030 in my final design.

UDIS is not a harware-driven flag to indicate over(under)run. Quote from Page 780 of RM0394 Rev 4 :

" Bit1 UDIS: Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

• – Counter overflow/underflow
• – Setting the UG bit
• – Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value

(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. "

Thanx, Peter

> UDIS is not a harware-driven flag to indicate over(under)run.

I never said that.

I said, that what you've call under/overrun, is in STM32 called Update. And then read the TIM chapter in RM to find all the references to the Update event, including the flag indicating its occurence in TIMx_SR, and the flag enabling interrupt upon it in TIMx_DIER.

Just read that chapter.

JW