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Can I use all peripheral in MP1 by only M4 code?

Jungho
Associate II

Hi.

Can I use all peripheral in MP1 by only M4 code? 

I couldn't find MP1 HAL Library for USB, Ethernet, SD Memory and etc.

For example, How can I use it if I want to use USB data write&read by M4 code?

Thank you.

Best regards.

1 ACCEPTED SOLUTION

Accepted Solutions
Olivier GALLIEN
ST Employee

Hi @Jungho​ , @Lukas Brückner​ ,

Access/ assignement and isolation are 3 differents concept in MP1.

I can go further if you need, but I just want to summarize that MP15 architecture is no designed to drive ETH and USB from M4 on both HW and SW side.

If nothing strictly prevent M4 to access ETH and USB peripheral, M4 sub-system is not sized to sustain high data rate interface ( no cache, very limited access to DDR )

ST is not delivering any validated stack on M4 for those IPs.

We clearly discourage customer to take this path.

@Jungho​  why do you want ETH and USB on M4 and not on A7 ?

Olivier

Olivier GALLIEN
In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

View solution in original post

5 REPLIES 5
Fee
Senior

Hi,

to see which peripherals can be used by which context (A7 Secure/Non-Secure and M4) you can have a look at this wiki page:

https://wiki.st.com/stm32mpu/wiki/STM32MP15_peripherals_overview#Internal_peripherals_overview

I'm afraid USB and Ethernet are just controllable by the A7 core(s) and therefore you will need to use them with linux.

Jungho
Associate II

Thank you for the reply.

I've seen the page before, but I didn't understand clearly last time.

And I thought that connected double bus line M4 and A7 by another bus line.

refer RM0436 / 122page (figure 1. Bus interconnect for STM32MP157)

If I want to use ETH or USB from M4 code, do I have to only access that through IPCC? Is there another way?

like this wiki page : https://wiki.st.com/stm32mpu/wiki/Coprocessor_management_overview#System_overview

Not an expert on the low level bus architecture but I can understand your confusion with the reference manual (the bus matrix seems to be connected). Also the ETZPC Peripheral is responsible for the isolation of the peripherals and for that the reference manual of the STM32MP157C (RM0436 Rev4) says that the ETH1 Peripheral should be able to be MCU seperated and therefore assignable to the M4 Core (Page 1121). The USB cannot be MCU isolated.

Seems to be an inconsistency between the wiki and the reference manual @Community member​ ?

Olivier GALLIEN
ST Employee

Hi @Jungho​ , @Lukas Brückner​ ,

Access/ assignement and isolation are 3 differents concept in MP1.

I can go further if you need, but I just want to summarize that MP15 architecture is no designed to drive ETH and USB from M4 on both HW and SW side.

If nothing strictly prevent M4 to access ETH and USB peripheral, M4 sub-system is not sized to sustain high data rate interface ( no cache, very limited access to DDR )

ST is not delivering any validated stack on M4 for those IPs.

We clearly discourage customer to take this path.

@Jungho​  why do you want ETH and USB on M4 and not on A7 ?

Olivier

Olivier GALLIEN
In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.

Thank you. @Fee (Community Member), @Community member (ST Employee).

Yes, I was confused by different information.

I see that M4 is a co-processor. I'll refer to it when I review it.

The reason I want ETH and USB on M4 and not on A7 because I don't have enough experience about developing it on the Linux.

The biggest reason is the project deadline. I don't have enough time for making by new method. 

To be more specific, I've gotten in the new project, so I have to choose new MCU.

I think that the requirement is enough to make new product on Non-OS this time. But my customer wants to make using OS it for the next generation product even if it's not this time. Because he doesn't want to pay again to make the next PCB.