SPI maximum clock frequency for STM32H5 MCUs devices when using PB13 and PB14 I/Os
Summary
This article includes SPI characteristics and clarification of maximum clock frequency when using PB13 and PB14. They are applicable for STM32H523xx, STM32H533xx, STM32H573, STM32H562xx, and STM32H563xx microcontrollers. The purpose of the article is to anticipate the updates that will occur soon in the “SPI characteristics” tables of the STM32H573xx, STM32H562xx and STM32H563xx datasheets (DS14258 Rev 2 and DS14121 Rev 2).
SPI interface characteristics
Unless otherwise specified, the parameters given in the SPI characteristic table are derived from tests performed under the ambient temperature. fPCLKx frequency, and VDD supply voltage conditions are summarized in the datasheet, with the following configuration:
- Output speed is set to OSPEEDRy[1:0] = 11
- Capacitive load CL = 30 pF
- Measurement points are done at CMOS levels: 0.5 x VDD
- I/O compensation cell activated
- HSLV activated when VDD ≤ 2.7 V
- VOS level set to VOS0
Refer to section “I/O port characteristics” in the STM32H5xx datasheet for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI).
Note: In the tables below, the terms "master" and "slave" have been replaced respectively by "controller" and "target". This is an intentional change to improve inclusive language, and will eventually be implemented in all documentation.
Table: SPI Characteristics for STM32H573xx, STM32H562xx and STM32H563xx microcontrollers (1*)
|
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Unit |
|
fSCK 1/tSCK |
SPI clock frequency |
Controller receiver mode 2.7 V <VDD< 3.6 V |
- |
- |
135/3(2*) |
MHz
|
|
Controller receiver mode 1.71 V <VDD< 2.7 V |
- |
- |
120/3(2*) |
|||
|
Controller transmitter mode 2.7 V <VDD< 3.6 V |
- |
- |
135/3(2*) |
|||
|
Controller transmitter mode 1.71 V <VDD< 3.6 V |
- |
- |
120/3(2*) |
|||
|
Target receiver mode 1.71 V <VDD< 3.6 V |
- |
- |
120 |
|||
|
Target transmitter mode 2.7 V <VDD< 3.6 V |
- |
- |
43/6(3*) |
|||
|
Target transmitter mode 1.71 V <VDD< 2.7 V |
- |
- |
41/6(3*) |
1*. Evaluated by characterization – not tested in production.
2*. When using PB13.
3*. When using PB14.
Table: SPI characteristics for STM32H523xx/STM32H533xx microcontrollers (1*)
|
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Unit |
|
fSCK 1/tSCK |
SPI clock frequency |
Controller receiver mode 2.7 V <VDD< 3.6 V |
- |
- |
135/3(2*) |
MHz
|
|
Controller receiver mode 1.71 V <VDD< 2.7 V |
- |
- |
120/3(2*) |
|||
|
Controller transmitter mode 2.7 V <VDD< 3.6 V |
- |
- |
135/3(2*) |
|||
|
Controller transmitter mode 1.71 V <VDD< 2.7 V |
- |
- |
120/3(2*) |
|||
|
Target receiver mode 1.71 V <VDD< 3.6 V |
- |
- |
120 |
|||
|
Target transmitter mode 2.7 V <VDD< 3.6 V |
- |
- |
43(3*)/6(4*) |
|||
|
Target transmitter mode 1.71 V <VDD< 2.7 V |
- |
- |
41.5(3*)/6(4*) |
1*. Evaluated by characterization – not tested in production.
2*. When using PB13.
3*. The maximum frequency in target transmitter mode is determined by the sum of tv(SO) and tsu(MI), which must fit into the SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a controller having tsu(MI) = 0 while Duty(SCK) = 50%.
4.* When using PB14.
Consider that PB13 and PB14 are special IOs for UCPD with limited speed (supporting Low speed output and medium speed).
The clock frequency is limited to 3 MHz when PB13 in controller output mode is used.
The clock frequency is limited to 6MHz when PB14 in target output mode is used. In this case, it is the value measured according to the datasheet conditions: IO speed/VDD/Load capacitance.
Tips
PB13 impact on controller mode:
- When using SPI2 in controller mode, PB13 limits the max clock frequency on SPI as indicated in the product datasheet.
- It is recommended to use PB10, PA9, PA12, or PD3 as clock output in controller mode if a high data rate is required.
- When using SPI2 in target mode and PB13 is used as clock, the max speed is not limited by PB13.
PB14 impact on target mode:
- If SPI2 is used in full duplex target mode, target output on PB14 limits the max data rate on SPI as indicated in the product datasheet.
- For high-speed communication in target mode, it is recommended to switch PB14 to input (PB14 by default in output mode when SPI2 is target). For this, software can enable the IO swap feature by using Bit 15 IOSWP (swap functionality of MISO and MOSI pins) in SPI_CFG2 register on the SPI2 interface (PB14 will be used as target input in this case).
