Workaround interfacing STM32F429 FMC with a TFT

Posted on November 19, 2016 at 11:02

If the additional control lines are free, i.e. not connected to anything else, you could try enabling their alternate functions to see if that makes reading start working.

Better yet, if those control lines are not in use, just wire your bad choice pins to the right pins and make sure the bad choices are configured as digital inputs.  The small additional load is unlikely to matter.

Posted on November 19, 2016 at 15:50

Hi Markt,

Thanks for the idea. It does seem to work (as in not crashing) but i am still not getting a read. Before I cut up traces on this prototype to re-route the 4 lines manually, I decided to replicate the setup on the STM32F407 disco. I have the FSMC up and writing, but I am still not getting LCD reads. The control lines are being toggled correctly now so i'm trying to figure out what I am missing. All my code is very similar to the STM32F103 tft sample. 

Posted on November 19, 2016 at 19:12

Here are my GPIO and FSMC inits 

void LCD_CtrlLinesConfig(void)

{

GPIO_InitTypeDef GPIO_InitStructure;

/* Enable GPIOD, GPIOE, GPIOF, GPIOG and AFIO clocks */

RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD |  RCC_AHB1Periph_GPIOE |

RCC_AHB1Periph_GPIOF, ENABLE);

/*-- GPIO Configuration ------------------------------------------------------*/

/* SRAM Data lines,  NOE and NWE configuration */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |

GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15 |

GPIO_Pin_4 |GPIO_Pin_5;;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;

GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;

GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_NOPULL;

GPIO_Init(GPIOD, &GPIO_InitStructure);

GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FSMC); //D2

GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FSMC);//D3

GPIO_PinAFConfig(GPIOD, GPIO_PinSource4, GPIO_AF_FSMC);//RD/NOE

GPIO_PinAFConfig(GPIOD, GPIO_PinSource5, GPIO_AF_FSMC);//NWE/WR

GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FSMC);//D13

GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FSMC);//D14

GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FSMC);//D15

GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FSMC); //D0

GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FSMC);//D1

GPIO_PinAFConfig(GPIOD, GPIO_PinSource7, GPIO_AF_FSMC);//CS - NE1

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |

GPIO_Pin_11 /* //RST*/ | GPIO_Pin_12  /*RS/A17*/| GPIO_Pin_11 | GPIO_Pin_14 |

GPIO_Pin_15;

GPIO_Init(GPIOE, &GPIO_InitStructure);

GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FSMC);

GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FSMC);

GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FSMC);

GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FSMC);

GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FSMC);

GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FSMC);

GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FSMC);

GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FSMC);

GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FSMC);

/* SRAM Address lines configuration */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;

GPIO_Init(GPIOF, &GPIO_InitStructure);

GPIO_PinAFConfig(GPIOF, GPIO_PinSource0, GPIO_AF_FSMC);

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 ;

GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;

GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_DOWN;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;

GPIO_Init(GPIOD, &GPIO_InitStructure);

}

void LCD_FMCConfig(void)

{

FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;

FSMC_NORSRAMTimingInitTypeDef FSMC_NORSRAMTimingInitStructure;

  /* Enable FMC clock */

  RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);

/*-- FMC Configuration ------------------------------------------------------*/

/*----------------------- SRAM Bank 3 ----------------------------------------*/

  /* FMC_Bank1_NORSRAM4 configuration */

  FSMC_NORSRAMTimingInitStructure.FSMC_AddressSetupTime = 5;

  FSMC_NORSRAMTimingInitStructure.FSMC_AddressHoldTime = 0;

  FSMC_NORSRAMTimingInitStructure.FSMC_DataSetupTime = 5;

  FSMC_NORSRAMTimingInitStructure.FSMC_BusTurnAroundDuration = 0;

  FSMC_NORSRAMTimingInitStructure.FSMC_CLKDivision = 0;

  FSMC_NORSRAMTimingInitStructure.FSMC_DataLatency = 0;

  FSMC_NORSRAMTimingInitStructure.FSMC_AccessMode = FSMC_AccessMode_A;

  /* Color LCD configuration ------------------------------------

     LCD configured as follow:

        - Data/Address MUX = Disable

        - Memory Type = SRAM

        - Data Width = 16bit

        - Write Operation = Enable

        - Extended Mode = Enable

        - Asynchronous Wait = Disable */

  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;

  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;

  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;

  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;

  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;

  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;

  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;

  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;

  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;

  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;

  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;

 //FSMC_NORSRAMInitStructure.FSMC_ContinousClock = FMC_CClock_SyncOnly;

  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &FSMC_NORSRAMTimingInitStructure;

  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &FSMC_NORSRAMTimingInitStructure;

  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);

  /* Enable FMC NOR/SRAM Bank3 */

  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);

}