Skip to main content
jjackbauer7
Associate III
April 10, 2013
Question

USB data FIFO map: question of newbie

  • April 10, 2013
  • 3 replies
  • 679 views
Posted on April 10, 2013 at 19:56

Hi all,

As I said previously, I am learning USB and reading and reading again the USB spec.

I want to understand the USB dta FIFO.

In fact in table ''Data FIFO access register map'', there is an address range.

For example for EP0; the range is ''

0x1000–0x1FFC

''

My question is: as it is a FIFO should be a set at a single address for read/write (as an example ''0x1000'') and not a range?

Thanks
    This topic has been closed for replies.

    3 replies

    Tesla DeLorean
    Guru
    April 10, 2013
    Posted on April 10, 2013 at 20:58

    The inferred behaviour is that it doesn't decode the low order address bits, thus a linear copy across a range, or repeated write to single address, both have the same effect of filling the FIFO.

    Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..
    Workalot
    Associate III
    December 18, 2015
    Posted on December 18, 2015 at 10:30

    A belated response to Clive1's gem on inferred FIFO behaviour. 

    Would also be inferred that the core maintains an internal pointer that increments on the write pulse? If so, what core activity or register manipulation would reset that pointer? That is, apart from GRSTCTL involvment.

    tsuneo
    Associate II
    December 18, 2015
    Posted on December 18, 2015 at 17:34

    > what core activity or register manipulation would reset that pointer?

    Write to FIFO size registers, GRXFSIZ, TX0FSIZ and DIEPTXFx

    Tsuneo