STM32F3xx Clock configuration

Hi to all,

this is my first project using a STM32F373 MCU, but I am not able even to let a LED blink.

I assume that system clock is not running as I get no response also enabling the MCO and check it with a scope.

For my clock initialization routine I used the cubemx code as base. Here is my code:

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/*-------------------------------- HSE - HSI Configuration -----------------------*/
 if(!HSEHSI)
 {
 if(!(RCC->CR & RCC_CR_HSION)) RCC->CR |= RCC_CR_HSION; // If HSI in not ON, just enable it
 while(!(RCC->CR & RCC_CR_HSIRDY));
 RCC->CR &= ~RCC_CR_PLLON; // Disable PLL
 RCC->CFGR &= ~RCC_CFGR_PLLSRC_HSE_PREDIV; // HSI as PLL source
 }
 else
 {
 RCC->CR &= ~RCC_CR_HSEBYP; // Disable HSE_BYPASS
 RCC->CR |= RCC_CR_HSEON; // Enable HSE
 while(!(RCC->CR & RCC_CR_HSERDY)); // Wait for HSE being ready
 RCC->CR &= ~RCC_CR_PLLON; // Disable PLL
 while(RCC->CR & RCC_CR_PLLRDY); // Wait for PLL disabled
 RCC->CFGR |= RCC_CFGR_PLLSRC_HSE_PREDIV; // HSE as PLL source
 RCC->CFGR &= ~RCC_CFGR_PLLXTPRE; // HSE not divided
 RCC->CFGR2 &= (RCC->CFGR2 & ~RCC_CFGR2_PREDIV) | RCC_CFGR2_PREDIV_DIV1; // Input clock not divided
 }
 RCC->CFGR = ((RCC->CFGR & ~RCC_CFGR_PLLMUL) | RCC_CFGR_PLLMUL9); // PLL = 9*HSE
 RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; // PLL as SYSTEM CLOCK
 RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_PLLXTPRE) | RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1; // HSE/PREDIV clock not divided for PLL entry
 RCC->CFGR |= RCC_CFGR_USBPRE_DIV1_5; // USB divided by 3
 RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_PPRE2) | RCC_CFGR_PPRE2_DIV1; // APB2 not divided
 RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_PPRE1) | RCC_CFGR_PPRE1_DIV2; // APB1 divided by 2
 RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_HPRE) | RCC_CFGR_HPRE_DIV1; // AHB not divided
 RCC->CFGR2 &= (RCC->CFGR & ~RCC_CFGR_MCO) | RCC_CFGR_MCO_SYSCLK; // Enable MCO
 RCC->CR |= RCC_CR_PLLON; // Enable PLL
 while(!(RCC->CR & RCC_CR_PLLRDY)); // Wait for PLL enabled
// FLASH->ACR = (FLASH->ACR &(~FLASH_ACR_LATENCY)) | FLASH_ACR_LATENCY_2; // Set FLASH latency = 2
 /*-------------------------------- LSE - LSI Configuration -----------------------*/
 if(!LSELSI)
 {
 if(!(RCC->CSR & RCC_CSR_LSION)) RCC->CSR |= RCC_CSR_LSION; //Enable LSI
 while(!(RCC->CSR & RCC_CSR_LSIRDY)); // Wait for LSI ready
 RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | RCC_BDCR_RTCSEL_LSI; // LSI as RTC clock
 }
 else
 {
 PWR->CR |= PWR_CR_DBP; // Disable RTC write protect
 if(!(RCC->BDCR & RCC_BDCR_LSEON)) RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_LSE) | RCC_BDCR_LSEON; // If LSE in not ON, just enable it
 while(!(RCC->BDCR & RCC_BDCR_LSERDY));
 RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | RCC_BDCR_RTCSEL_LSE; // LSE as RTC clock
 }
 RCC->CIR = 0x00000000; // Disable all interrupts�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?�?

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Someone encountered this problem already?

Do I make some mistakes?

Thank you

Freya