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msinger
msinger
Associate
June 26, 2014
Question

STM32F303 ADC/DMA

Posted on June 26, 2014 at 19:25

I am using all 4 ADC's with 4 channels used on each. ADC 1 is on DMA1 and ADCs 2-4 have channels on DMA2.  All 4 ADC's run off timer15 at 1Khz.  The problem I am having is that I only get DMA interrupts for ADC 3,4 a few times and then not at all.  If I change the DMA priority so that it is higher on ADC4, then I only get ADC1 and ADC4.  DMA2 doesn't seem to be arbitrating among the channels.   It doesnt effect it if the IRQ priority on each of the DMA interrupts is the same or different.

Suggestions?

#stm32-adc-dma
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5 replies

Tesla DeLorean
Tesla DeLorean
Guru
June 26, 2014
Posted on June 26, 2014 at 22:32

Suggestions?

Is the DMA indicating any error/fault condition? The IRQ typically doesn't fire unless the DMA is actually functioning

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raptorhal2
raptorhal2
Lead
June 26, 2014
Posted on June 26, 2014 at 23:05

ST needs to step into this discussion to clarify. According to the reference manual, Rev 3 Section 11.4.7, DMA2 is not designed to arbitrate among channels.

DMA2 controller

 

 

The five requests from the peripherals (TIMx (x= 6,7,8), ADCx (x=2,3,4), SPI/I2S3, UART4, DAC_Channel[1,2] ) are simply logically ORed before entering the DMA2, this means that only one request must be enabled at a time. Refer to Figure 25: STM32F303xB/C and STM32F358xC DMA2 request mapping.

The reference manual says DMA 1 can arbitrate between channels. The referenced figures show a similar arrangement of OR'd peripherals for each channel for both DMAs. Confusing, no ?

Cheers, Hal

raptorhal2
raptorhal2
Lead
June 26, 2014
Posted on June 26, 2014 at 23:12

If you are not chained to the F303, the F4 has streams to take care of this sort of problem.

Cheers, Hal

Tesla DeLorean
Tesla DeLorean
Guru
June 26, 2014
Posted on June 27, 2014 at 01:18

Will push to moderation.

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msinger
msingerAuthor
Associate
June 27, 2014
Posted on June 27, 2014 at 13:31

Not sure about the comments on the DMA engine or'ing the channel sources together, but if I run ADC's 1 & 2 off of timer 15, then use separate timers for ADCs 3 &4 (3 timers total), then I get all the DMA interrupts.

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