SHPRx System handler priority register won't set to 0xFF

[markf_engineer]

Posted on May 31, 2017 at 03:37

I’m debugging some low-level code.  The STM32L471 hardware is not configuring properly per the code.  I’m configuring the System handler priority registers (SHPRx).  See ST manual PM0214 programming manual or ARM architecture reference.  The programming manual states the priority of each handler is a range from 0 to 255 (0xFF).  When I try to set a value of 0xFF, the hardware only sets the value to 0xF0.  This is not the published range per the ARM and ST docs.

In my example code, the SHPR2 register isn’t setting to 0xFF for PRI11; it only sets the register to 0xF0.  Same is true for SHPR3 register isn’t setting to 0x40FF0000; it only sets to 0x40F00000.

I’ve checked ARM and ST literature; they all indicate that each field supports a priority value from 0 to 255 (0xFF) so I should be able to set PRI11 and PRI14 to 0xFF.  Please advise if you why the ST part is failing to function as documented?  Workaround?

See screenshots.  Does anyone have any insight about why these registers aren’t working per the literature?

[markf_engineer]

Posted on May 31, 2017 at 04:25

The answer was found, but the docs aren't easily searchable and the reference is obscure.  ST reference manual RM0392 page 310, section 11.1 states the NVIC has 16 priority levels, 4 bits.  Indirectly this answers the question, since this the priority of the SHPRx is an NVIC configuration.  The docs should be more specific to indicate that the SHPRx registers only support the high nibble and 16 priority levels.  The bit usage of SHPRx is not described in the docs at all, and until you experiment you'd never know the high nibble is only used.  The reference manual has no instructions on how use SHPRx, SHPR1, 2, or 3 in the manual.