QuadSPI Single SPI mode IO2 state

Hi frackers,

This is normal and just fine, the write protect pin simply protects writes to the memory, not the registers of the flash chip.

When you enable QPI by writing to the status register (don't forget to write enable first), IO2 & 3 will then change to the correct mode.

If you're using the HAL, configuring the QSPI_CommandTypeDef with the correct mode's (QSPI_INSTRUCTION_1_LINE, QSPI_ADDRESS_1_LINE, QSPI_DATA_1_LINE etc), the pins will be configured correctly automatically for that mode.

Example to setup to write in Single SPI mode:

QSPI_CommandTypeDef cmd = {
			.Instruction = QSPIF_PROG,
			.Address = writeAddr,
			.InstructionMode = QSPI_INSTRUCTION_1_LINE,
			.AddressMode = QSPI_ADDRESS_1_LINE,
			.AddressSize = QSPI_ADDRESS_24_BITS,
			.DataMode = QSPI_DATA_1_LINE,
			.NbData = lengthToWrite,
	};
// Send the command (this sends the instruction and address value)
HAL_QSPI_Command(&hqspi, &cmd, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
 
// Write the data (this transmits the data of length cmd.NbData)
HAL_QSPI_Transmit(&hqspi, data, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);

Just reconfigure the pins connected to IO2 and/or IO3 to GPIO outputs momentarily, then you can assign any state to them. No need to disable the QSPI interface for that. One write to the MODER register, that's it.

BTW: Check the flash's data sheet carefully. The WP input does not (at least on some chips) write protect the memory array by itself, but protects the block write protection flags from beeing changed. So, if no block protection is engaged (usually the default when shipped), the memory array is writeable regardless of the level on the WP pin.

E. g. W25Q128FV: "The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware protected. The /WP pin is active low."