Posted on August 04, 2017 at 22:08The original post was too long to process during our migration. Please click on the attachment to read the original post.
The way you chose to handle the change of cycle and width is quite anorthodox.
The PWM generation is normaly handled by the hardware.
If you want to change the cycle and width you must put the new values to ARR and to CCR and wait tothe next update event of the counter to load the new values
If you dont want to wait until the next update event you have the option fto set the EGR.UG flag to trigger an imediate update with new values.
In your code every ttime you call the
startPWM_Test
is like to reinitialise the timer.
It stops counting, loads the same values and again starts etc. .
If you want clean pwm pulses ,
just eliminate this code
//TIM2->CNT = 0;
if
(( TIM2->
CR1
& TIM_CR1_CEN ) == 0)
// first pass turn on timer and
cfg
, otherwise just load CCR2 and ARR to shadow registers
This is demo code extracted from the main project to show the issue in a simplified manner. I was originally re-initializing the clock on each pass before I realized that those registers were shadow copied. I changed the code with the
if
(( TIM2->
CR1
& TIM_CR1_CEN ) == 0) statement so the timer is initialized only if the counter is off.
