NRST Reset functionality on the STM32F205VCT

> 1) The reset 'architecture', and how it links into / controls other parts of the processor (especially ports & outputs).

From RM0033:

> A system reset sets all registers to their reset values except the reset flags in the clock

> controller CSR register and the registers in the Backup domain (see Figure 4).

> A system reset is generated when one of the following events occurs:

> 1. A low level on the NRST pin (external reset)

[...]

Throughout the RM, the reset state of all registers is given in the description of those registers, including GPIO.

I don't quite understand what exactly do you mean by the remaining questions. There may be synchronous paths in the reset mechanism and the mechanisms between the internal registers and pins, but upon reset the system clock in RCC is also switched to HSI which is switched on upon reset - see reset value of RCC_CR and RCC_CFGR. Worst case HSI startup time is given in DS.

You may want to ask whether the GPIO reset is asynchronous, but that's a question you are not likely to be answered here. Note, that this is a primarily user-driven forum, so more in-depth question should be asked ST directly.

JW

"As this is a safety related system"

It always scares me when people say this, and in the same breath indicate they haven't really read the Reference Manual, and Data Sheets, which definitely contain diagrams and logic for the circuit.

https://www.st.com/content/ccc/resource/technical/document/reference_manual/51/f7/f3/06/cd/b6/46/ec/CD00225773.pdf/files/CD00225773.pdf/jcr:content/translations/en.CD00225773.pdf

The chip POR depends on the VDDA pin.

Personally I think the pulse width is far too short, you'd want to seriously consider something monitoring externals supplys (all of them if multiple rails and ramp times), that can threshold, and hold the NRST low for hundreds of milliseconds.

Also for ARM systems, do NOT drive the NRST high using push-pull drivers.

#RTFM​