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Mike Forster
Mike Forster
Associate
April 4, 2017
Solved

LSE Oscillator on STM32F769

  • April 4, 2017
  • 8 replies
  • 4228 views
Posted on April 04, 2017 at 18:32

I have a custom board with a STM32F769 and I am having problems getting the low speed LSE oscillator running. I am using CubeMX 4.19 to generate the low level code. In order to get the oscillator to run I need to set the drive strength to high with the LSEDRV bits in the RCC_BDCR.

However the code produced by CubeMX calls HAL_RCC_OscConfig() before setting the drive strength. The call to HAL_RCC_OscConfig() fails with a timeout because the LSERDY bit never gets set, because the oscillator isn't running.

I can add

__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);

to stm32f7xx_hal_rcc.c but this will get over written next time I generate code from CubeMX.

As a side issue the reference manual suggests at 5.3.20 that the LSEDRV bits are not part of the backup domain but I don't seem to be able to write to them until the backup domain write accesses have been enabled.

Any ideas what to do next? I know I could change the 32.768kHz to a low capacitance device that works with low drive strength but I am looking for a software solution.

Thanks,

Mike

    This topic has been closed for replies.
    Best answer by kormoczi
    Posted on October 05, 2017 at 16:35

    Hello!

    Are you sure that the generated code is correct?

    In my project the LSEDRV is not set with __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH), because

    at that point there is no write access to Backup domain.

    I have solved this bug by moving __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH)

    to right after the 'Backup domain Write protection disable' code section in the 

    HAL_RCC_OscConfig function

    .

    I think this is a bug in

    STM32CubeMX which has to be solved.

    8 replies

    Tesla DeLorean
    Tesla DeLorean
    Guru
    April 4, 2017
    Posted on April 04, 2017 at 19:09

    STM32 devices have historically been very intolerant of 9 and 12pF crystals (slow to start, don't start)

    You will get far fewer headaches using 6-7pF crystals.

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      Nesrine M_O
      Nesrine M_O
      Associate
      April 4, 2017
      Posted on April 04, 2017 at 19:13

      Hi

      Forster.Mike

      ,

      I suggest you to have a look to

      http://www.st.com/content/ccc/resource/technical/document/application_note/c6/eb/5e/11/e3/69/43/eb/CD002216pdf/files/CD002216pdf/jcr:content/translations/en.CD002216pdf

      application note and the

      http://www.st.com/content/ccc/resource/technical/document/application_note/b0/5c/ba/b2/cb/10/41/dd/DM001645pdf/files/DM001645pdf/jcr:content/translations/en.DM001645pdf

      user manual to have

      more details on compatible crystals and hardware techniques on PCB.

      -Nesrine-

      Mike Forster
      Mike ForsterAuthor
      Associate
      April 5, 2017
      Posted on April 05, 2017 at 15:00

      Thanks Nesrine and Clive but I am familiar with AN2867. Looking at Table 7 I see that there are four 12.5pF crystals recommended for the F7. Okay, I am not using one of them but it should work, and indeed does work if I set high drive strength. The problem is a bug in CubeMx that checks the LSE is operating before setting the drive strength.

      In fact I have the 12.5pF MicroCrystal CM7V-T1A on the board but have ordered some 6pF ones to try out.

      Mike

      Nesrine M_O
      Nesrine M_O
      Associate
      April 5, 2017
      Posted on April 05, 2017 at 15:29

      Hi

      Forster.Mike

      ,

      The issue regarding the reference manual and the CUBEMX code generation has been reported internally for check.

      -Nesrine-

      stm32cube-t
      stm32cube-t
      ST Employee
      October 4, 2017
      Posted on October 04, 2017 at 17:11

      Hello STM32CubeMX is now fixed.

      You can check it out by :

      1. Enabling LSE in crystal mode

      2. Enabling RTC peripheral

      3. On the clock tree select LSE as RTC clock :

      0690X00000608U3QAI.png

      4. Open from the configuration tab, the RCC configuration window and check LSE drive option:

      0690X00000608U8QAI.png

      5. generate code and find proper sequence of initialization:

      void SystemClock_Config(void)

      {

        RCC_OscInitTypeDef RCC_OscInitStruct;

        RCC_ClkInitTypeDef RCC_ClkInitStruct;

        RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;

          /**Configure LSE Drive Capability

          */

        __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_HIGH);

          /**Configure the main internal regulator output voltage

          */

        __HAL_RCC_PWR_CLK_ENABLE();

        __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);

          /**Initializes the CPU, AHB and APB busses clocks

          */

        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE;

        RCC_OscInitStruct.LSEState = RCC_LSE_ON;

        RCC_OscInitStruct.HSIState = RCC_HSI_ON;

        RCC_OscInitStruct.HSICalibrationValue = 16;

        RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;

        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)

        {

          _Error_Handler(__FILE__, __LINE__);

        }
      Tesla DeLorean
      Tesla DeLorean
      Guru
      October 4, 2017
      Posted on October 04, 2017 at 17:24

      Wouldn't this be an ideal case where you plug in crystal characteristics and capacitor values, and have the software perform a 'will it blend' kind of test, and select the appropriate drive settings, etc.?

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      Mike Forster
      Mike ForsterAuthor
      Associate
      February 1, 2018
      Posted on February 01, 2018 at 13:53

      kermeci is correct that the so called fix to CubeMX doesn't work. As he says the code generated writes to the RCC_BDCR register while it is in Read only mode.

      Mike

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