Instructions SVC (ARM)

Posted on September 29, 2015 at 22:38

Probably because it saves a lot of silicon, and state information that would otherwise need to be preserved.

My understanding on the M3/M4 is that you have to use the LR to determine which stack to use, and then fish around on that for the PC, and extract the SVC# from the instruction.

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/SVC_Handler%20fails%20badly%20%20-%20hardfaults&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=454

Current link to mentioned document

https://www.arm.com/files/pdf/Cortex-M3_programming_for_ARM7_developers.pdf

Posted on September 30, 2015 at 02:57

Thanks for the quick response.

Silicon saved - wake up to do bold code :).

Posted on September 30, 2015 at 14:11

It seems no one teaches processor architecture in school anymore.  The SVC supervisor call instruction is not a ''crutch'' but a time proven method dating back to architectures developed for the earliest multitask machines in the early 1960s.  Most all the major operating systems used the same idea of a supervisor call instruction followed by a block of parameters  (the PDP-10 UUO, CDC 6000 XJ exchange jump, PDP-20 JSYS are just a few examples).

Load the return address in the frame pointer and instantly have access to all the parameter calls in a reliable and well-defined format.  Pop the frame by changing the return address with a single ADD.  All very fast and stack (a scarce resource in those days) efficient.

  Jack Peacock

Posted on September 30, 2015 at 19:08

It seems no one teaches processor architecture in school anymore.

I don't even know what track that would be under these days, I took the EE route rather than CS, and to be honest I never took a course that covered this in much detail, even with the IC Design stuff. I've personally read stuff by Patterson, Hennessy, Ditzel, Wilson and Furber, and had occasion to sit in Dave Ditzel's office when he was at Transmeta. When I was initially working with 6502, Z80 and 68000 there was a lot of Leventhal and Zaks.

ARM's done a lot of elegant/clever stuff, it can look a little rough at the edges at times, but by slightly shifting something into simple code sequences 100s of gates and lots of hazards are avoided. A lot of other architectures erect lots of fences to stop you from doing something stupid, or create complexity and bubbles in the pipelines.

Posted on September 30, 2015 at 20:55

In the 70s there were processor architecture classes at a few places but mostly the subject came up when learning assembly.  Studying architectures was a hot topic during the days of bit slice design in the 70s where it was relatively easy to roll your own instruction set.  I still have my cherished ''Mick and Brick'' processor design book on how to build your own CPU with AMD bit slices.  All done with RTL and FPGAs now but the principles remain the same.

ARM's ''big.LITTLE'' designs come directly from Seymour Cray and his CPU/PPU distributed I/O for CDC and Cray machines 50 years ago.  IBM borrowed the same idea for I/O channels in later 360 and on to the 370 series.  The memory mapped I/O homogeneous memory space in ARMs came from DEC and the PDP-11, where I/O was mapped into high memory to save cost and simplify instruction set.  The ARM THUMB2 instruction packing was another Cray invention for the 60-bit CDC-6000, where variable length instructions were packed into words.  Even the whole RISC concept used by ARM came from IBM research and what's now known as the PowerPC.

Too bad the historical perspective is being lost.  Understanding why an ARM CPU is designed in a certain way makes sense if you recognize it's roots from IBM, DEC and especially Cray's genius in CPU designs.

  Jack Peacock

Posted on October 01, 2015 at 02:49

That's actually what I wanted to do. Free interrupt control, without depending on the kernel mode.

Вот �?об�?твенно что �? хотел �?делать. Свободное управление прерывани�?ми, без зави�?имо�?ти от режима �?дра.

*.s,  GCC,  arm,  

Cortex-M3, EmBitz 0.40

 .globl    SVC_Handler

 .type    SVC_Handler, %function

SVC_Handler:

            mrs     r0, psp

            tst       lr, #4

            bne     __step1

            mrs     r0, msp

__step1:

            ldr       r0, [r0, #24]

            ldrsb   r0, [r0, #-2]

            tbh     [pc, r0, lsl #1]

SVC_Table:

    .hword   ((__EnableIRQS - SVC_Table)/2)

    .hword   ((__DisableIRQS - SVC_Table)/2)

///All this mess from the beginning of work interruptions - is required for the function.

/// I relied that it is easier to obtain. Otherwise, for small operations get very fat.

///В�?ё �?то безобразие от начала работы прерывани�? - требует�?�? дл�? выбора функции. 

///Я ра�?�?читывал что оно проще получит�?�?. Иначе дл�? мелких операций получает�?�? очень жирно. 

__EnableIRQS:

            mov     r3, #0x1F

            and      r0, r1, r3 

            mov     r3, #0x1

            lsls r2, r3, r0 

            lsrs       r0, r1, #5

            lsls r0, r0, #2

            mov     r3, #0xE100

            movt    r3, #0xE000

            str        r2, [r3, r0]  

            bx        lr

__DisableIRQS:

            mov     r3, #0x1F

            and      r0, r1, r3 

            mov     r3, #0x1

            lsls r2, r3, r0 

            lsrs       r0, r1, #5

            lsls r0, r0, #2

            movw    r3, #0xE180

            movt      r3, #0xE000

            str        r2, [r3, r0]  

            bx        lr

 .size SVC_Handler, . - SVC_Handler

*.h 

__attribute__( ( always_inline ) ) static inline NVIC_EnableIRQS(IRQn_Type IRQn)

{

__asm volatile(''mov r1, %[IRQ] \n\t''

               ''SVC  0x0       \n\t''

               :

               : [IRQ] ''r'' (IRQn));

}

__attribute__( ( always_inline ) ) static inline NVIC_DisableIRQS(IRQn_Type IRQn)

{

__asm volatile(''mov r1, %[IRQ] \n\t''

               ''SVC  0x1       \n\t''

               :

               : [IRQ] ''r'' (IRQn));

}

It turns out 16 cycles in the kernel interrupt SVC, to compute constant - which is lost ...

Получает�?�? 16 тиков �?дра в прерывании SVC, дл�? вычи�?лени�? кон�?танты - котора�? потер�?ла�?ь...

Смы�?л перевода может изменить�?�?.

Posted on October 10, 2015 at 18:30

__attribute__( ( always_inline ) ) static inline NVIC_DisableIRQS(IRQn_Type IRQn)

{

__asm volatile(''mov r1, %[IRQ] \n\t''

               ''SVC  0x1       \n\t''

               :

               : [IRQ] ''r'' (IRQn));

}

I can not figure out how to force the GCC enter the body functions online with ready data R1, want to get rid of the intermediate command ''mov r1,% [IRQ] \ n \ t''.

�?е могу пон�?ть, как принудительно за�?тавить GCC входить в тело онлайн функции �? уже готовыми данными в R1, хочу избавить�?�? от промежуточной команды ''mov r1, %[IRQ] \n\t'' .