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Torsten Jaekel
Torsten Jaekel
Associate III
May 8, 2019
Question

I2C with 5 MHz - possible?

  • May 8, 2019
  • 5 replies
  • 3164 views

If I understand STM32H7xx datasheet, I2C peripherals support up to 1 MHz (FM, FM+), 'officially'.

I would need an I2C with 5 MHz SCL clock.

I tried and have 'overclocked' I2C with 2 MHz which works fine.

Based on the clock configuration (e.g. a 50 MHz PCLK), it should be potentially possible to configure a much higher frequency.

Forget the fact the 5 MHz and very small pull-ups needed the STM cannot directly drive SDA and SCL.

My question is:

if the clock configuration allows to set a I2C SCL clock to 5 MHz - should it work?

Could I step into region with timing constraints (violations) or should the I2C signals be still OK, all internal logic still working properly?

Is the limitation to FM/FM+ (1 MHz) only due to the fact, that HS mode (greater 1 MHz) is actually based on sending a Master Code, change **** to HS and RESTART with a high speed I2C transaction?

(for this I have a working solution).

Thank you for any comments running I2C with 5 MHz SCL.

Torsten Jaekel

This topic has been closed for replies.

5 replies

MikeDB
MikeDB
Senior II
May 8, 2019

Use an LTC4311 instead of pull-up resistors and you'll be in with a chance without external buffers. I'm running a H750 at just over 3MHz and it's clean. Only way to see if it fails at higher speeds is to try it.

Torsten Jaekel
Torsten JaekelAuthor
Associate III
May 8, 2019

Thank you,

LTC4311 supports only up to 400KHz. I would select a PCA9306 as I2C level shifter (bandwidth up to 200MHz). Just: I've checked to use I2C porgrammable potentiometers as pull-ups: their bandwidth is soooo bad. And they do not support pretty high current.

Let's assume, for 5 MHz I2C I had to use pull-up resistors with 200 Ohm (it depends on all capacities: cables, drivers, chips on bus, input capacities) and 1V8 logic: 9 mA must be drawn.

I think, regular external pull-ups are better in terms of bandwidth (e.g. 0603 SMT)

MikeDB
MikeDB
Senior II
May 8, 2019

Oh it goes well beyond the specced frequency especially with a few tricks, as of course you are doing with the H7 series. If you prefer buffers then no problem but I would still look into active pullups even with those if you want the fastest possible response.

S.Ma
S.Ma
Principal
May 8, 2019

at 5 MHz, it's no longer I2C spec and probably outside the datasheet guaranteed operating range (at your own overclocking risk)

Now even if in theory you could go to 5MHz (Master mode?), the cell may have analog glitch filters in place which are asynchroneous.

This is used by I3C which high speed relies on spike filters to be backward compatible with I2C legacy slaves...

https://en.wikipedia.org/wiki/I3C_(bus)

Why not using USART at 5MHz?

Torsten Jaekel
Torsten JaekelAuthor
Associate III
May 8, 2019

True, outside existing specs. (3.4 MHz is max as I know). It is for testing such chips also in terms of upper limits.

Good point with involved de-glitchers and spike filters - thank you, I had to study datasheet again.

The beauty of the STM32H7 I2C is: I can configure everything, pulse duration, duty cycle, rise and fall time (I think). So, all other aspects such as level shifting, very strong (small) pull-ups, capability to drain high current (>= 10 mA) is additional topic which I want to handle with external components.

OK, I will give it a try and verify resulting signals.

Thank you.

Torsten Jaekel
Torsten JaekelAuthor
Associate III
May 9, 2019

I've checked the datasheet and the advice to check the Digital and Analog Filter involved, I came to following conclusion:

a) in case the Analog Filter is enabled (max. 260 ns delay, spikes/pulses filtered with this duration or faster) - it results in max. 3.8 MHz possible

b) if I keep Analog Filter disabled (DNF=1) I need 16x the 5 MHz I2C SCL clock rate as I2CCLK - 80 MHz internally to I2C block

c) if Digital Filter is enabled, the main contribution comes from tSYNC1 and tSYNC2 (each 83.3 ns with 48 MHz I2CCLK), plus each 1 SCLH and SCLL,

resulting in 4.8 MHz max.

So, Analog Filter must be off, Digital Filter maybe on or even off, and the internal I2CCLK, i2c_ker_ck, potentially as 80 MHz.

It might work but eventually bit errors can be seen.

An external driver/level shifter might be needed anyway (below 20 mA current due to pull-ups) and a careful PCB design (short traces, low capacity).

Thanks for the great hint.

I'll give it a try.

Torsten Jaekel
Torsten JaekelAuthor
Associate III
May 10, 2019

Update:

I have tried and tested, with a scope on I2C (and 270R pull-up, but no cable and chip):

I can see 7.1 MHz SCL working

So, I can configure 7.1 6.25 5.59 4.98 4.55 4.17 ... MHz as SCL clock.

The key is: disable analog filter, configure the digital filter (e.g. with delay 0) and tweak signal via the setup and hold time.

It seems to work what I need, just to test against/with the real chip on the other end.

(all results for now as just what comes out to scope).

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