GPIO configuration gitches

Posted on May 17, 2011 at 12:27

Hi lanchon,

I suggest you to test it on your board and let me know aboutwhat you will find. By the way I invite you to read : ''

http://www.st.com/stonline/books/pdf/docs/14418.pdf

'' Safe GPIO port configuration in STR7xx devices we made for our STR7 devices having more or less some similar features as STM32 you case is described in Table 42, but we have to check-it on STM32 :|

Cheers,

STOne-32

Posted on May 17, 2011 at 12:27

hi,

if you switch a GPIO pin from an input mode to an AF output mode, and the corresponding ODR bit has the opposite value of the output signal sent by the selected AF, is it guaranteed that no glitch will be observed? (ie, could the ODR bit briefly drive the pin?)

thanks!

Posted on May 17, 2011 at 12:27

Thanks for the AN pointer. I'm afraid something like this can't be tested, it's either guaranteed by design or it isn't. I'll have to code to avoid the glitches as if the problem were real.

(users of I2C might be affected by this.)