I haven't tried that, but:
I've tried to put SDRAM on a daughterboard on a Nucleo 144 board. The track lengths were (at best) uncontrolled. It wasn't really stable.
Now with dynamic RAM, I think the timing is picky.
With static ram, a display chip (S1D13517) on the same board, connected much the same way, was (and is) stable, with no special desire to make the track lengths identical. (look at the schematics for the disco boards with dynamic memory, they mention track length equalization on dynamic memory.
Static memory timing is lots easier to tweak.
when I used FPGAs, I used an SPI interface with read/write registers, which worked well enough.
You had to be a bit careful with VHDL to get it to work right, but it's been pretty reliable.
Why do you need to memory map it, and could you put it on the processor board and take the FPGA outputs/inputs off that? At best, I'd put it one layer above, but I'd use 22 or 33 ohm 0402 damping resistors.
