Clock enable for SWD ports (STM32G0)

I'm a bit confused about the necessity of clocking the SWD ports using STM32G0B1 chip.

There is a I/O port clock enable register (RCC_IOPENR) that enables the functioning of each of the GPIO ports (Port A - Port F), its reset state is all zeroes, so no port is clocked (including Port A, which pins 13-14 in the "alternate function" mode are SWDCLK/SWDIO ports). But the debugging via STLink seems to work in this default configuration. And the actual RCC_IOPENR register state still contain all zeroes during run time (so port A is still not clocked).

I didn't find any mentions of such an exception made for these particular pins in the RM.

If in CubeIDE I explicitly mark these ports as SWD ports, it then generates the code which enables the Port A clock. But if I comment out it, nothing changes, debugging works either way.

So, are these pins clocked separately from the rest of the port A pins? If not, is port A always clocked? And if yes, can I use other alternate functions on these pins without clocking the whole port A?