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What’s new in STM32CubeMX

Maxime_MARCHETTO1
Community manager

STMicroelectronics has released new versions in STM32Cube ecosystem, expanding STM32CubeMX support to more STM32 products and enabling configuration of innovative on‑chip IP for smarter, more efficient embedded designs.

The new release brings STM32CubeMX support for the latest STM32H5, STM32U3, and STM32WBA2 devices, helping developers quickly start new designs and reuse existing workflows across a growing STM32 portfolio.

STM32Cube v1.22 also adds configuration support for two advanced peripherals on selected STM32 devices:

  • PLAy (Programmable Logic Array) provides a small, configurable logic fabric on‑chip, ideal for custom glue logic, simple state machines, and deterministic event detection. By wiring internal events and external GPIO signals directly into PLAy, applications can react in hardware with cycle‑accurate timing, offloading the CPU and often eliminating external logic components.

The PLAy is supported on latest STM32H5E4/5F4 and STM32H5E5/5F5 product lines

  • HSP (Hardware Signal Processing) targets real‑time signal processing at very low power. It offloads filtering, spectral analysis, and feature extraction for continuous sensor streams (such as vibration, audio, or current sensing) to a dedicated hardware engine, allowing the main core to stay in low‑power modes until meaningful events are detected.

HSP is now available on new STM32U3B5/3C5 product lines.

Together, PLAy and HSP enable more responsive, efficient, and compact embedded systems by combining fast, deterministic control logic with rich, pre‑processed sensor information.

On the MPU side, STM32CubeMX now supports new configuration (M33-TD) of STM32MP2 devices, enabling developers to manage the Arm Cortex‑A35 as coprocessor from the Arm Cortex‑M33 core (booting on Cortex-M33 Trusted Domain flavor) on both evaluation and discovery boards. The release integrates with the newly available OpenSTLinux 6.2, which adds key capabilities such as STM32MP15 PSCI OSI, STM32MP2 A35‑TD PCIe Endpoint support, and GPU OPP management, and completes the Cortex‑M33 Trusted Domain flavor for mass‑market applications (including secure boot, system reset requests from either Cortex‑A35 or M33, and early panel splash screen driven by a non‑secure Cortex‑M33 application).

Additional resources


First published on Mar 23, 2026

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