What SPI clock frequencies are REALLY supported on STM32H753xI?

[TwelveSquared]

Regarding supported SPI clock frequencies:

The STM32H753xI datasheet speaks of various miracles; e.g., page 48 says, "The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI6) that allow communicating up to 150 Mbits/s in Master and Slave modes..." and page 193 mentions test conditions of Master Mode SPI clocks of 90 MHz to 133 MHz in Master Mode.

But, experimenting with STM32CubeMX, I don't see how the SPI peripheral can be configured for >24 MHz (SPI 1,2,3) or >32 MHz (SPI 4,5,6).

So, what's reality here?

[berendi]

SPI clock source (spi_ker_ck) can be set to various sources.

Check Figure 45. Top-level clock tree and Figure 51. Kernel clock distribution for SPIs and SPI/I2S in the reference manual.

To achieve 150 Mbits/s, some PLL outputs must be set to 300 MHz, and selected in the respective Kernel Clock Configuration Register (RCC->D2CCIP1R or RCC->D3CCIPR).

If you are lucky, CubeMX will generate code that actually sets the frequencies right. If it can't, then setting up PLLs through the RCC registers will certainly work.

Don't forget to set the correct VOS level, GPIO OSPEED to the highest possible value, and don't expect it to just work over DuPont jumper wires.

[Tesla DeLorean]

>>So, what's reality here?

Reality here is that you should put CubeMX down for a while and digest the Reference Manual. It is a complicated part, with many options, and means to route clock sources, you really need to get an overview of the plumbing, and drill down to the peripherals of interest.

I'd swear there is a big chart giving peripherals, clock sources, and maximum clocking rates for the xyz_ker_ck of each peripheral unit.

If the face page of the Data Sheet says it can hit X MHz clock rate, that's usually a bankable number with all the clocks, plls and assorted sources at their maximal settings.