STM32H757 (Dual-Core): M2M DMA interrupts greyed out in NVIC2 (M4 core) in STM32CubeMX
Hi everyone,
I am working on a dual-core project using the STM32H757Xi and running into an issue with STM32CubeMX regarding NVIC interrupt assignment for the Cortex-M4 core.
Here is my setup and the problem I am facing:
-
Microcontroller: STM32H757Xi
-
Toolchain: STM32CubeIDE v1.19
-
Goal: Configure two Memory-to-Memory (M2M) DMA channels assigned to and running on the Cortex-M4 core.
Issue details:
-
In CubeMX (under System Core -> DMA), I created two M2M channels: DMA2 Stream 6 and DMA2 Stream 7.
-
I also tested the exact same configuration using DMA1 Stream 6 and DMA1 Stream 7.
-
In both cases, when I check the NVIC settings, the Interrupt Request (IRQ) checkboxes and priority settings for these streams are only active under NVIC1 (Cortex-M7). Under NVIC2 (Cortex-M4), the corresponding IRQ checkboxes are completely greyed out and disabled.
Because CubeMX thinks these interrupts belong to NVIC1, it generates the DMA interrupt handlers in stm32h7xx_it.c for the M7 core context instead of the M4 core context.
Currently, I have to manually enable the IRQs via NVIC_EnableIRQ() in code and add the missing IRQHandler functions to the M4 source files manually. However, every time I regenerate code from CubeMX, I have to re-check and clean up the generated files, which is tedious and error-prone.
My questions:
-
Is there a trick or specific workaround in CubeMX to force these M2M DMA IRQs to be enabled under NVIC2 for the M4 core?
-
Has anyone tested this behavior in newer releases of STM32CubeIDE / CubeMX? Is this known behavior/bug resolved in a version newer than 1.19?
Any insights or workarounds would be greatly appreciated!
Thanks in advance.
