STM32H725 ADC1/2 run at half the configured speed?!

[Kolja Waschk]

Hi,

I'm currently setting up ADC1/2 of STM32H725IGx, using STM32CubeMX 6.3.0 with FW_H7_V1.9.0. They are configured to run at async ADC clock, which is about 126 MHz defined in CubeMX Clock Configuration, divided by 4 => 31,5 MHz.

However, sampling and conversion takes twice as long as expected!

When stepping through HAL initialization, I found that it (in ADC_ConfigureBoostMode()) computes the actual ADC frequency for determining the BOOST bits setting. It starts with 31,5 Mhz but then concludes as follows:

...

#if defined(ADC_VER_V5_3) || defined(ADC_VER_V5_V90)

 freq /= 2U;

...

with freq==15.75 MHz?!?

This would explain my observations. But what to do? CubeMX seems to calculate and check with wrong factors. It won't allow me to double the input frequency, telling me that fADC would be exceeded (but 31,5 MHz is below 50 MHz!)

Thanks for your comments,

Kolja

[Kolja Waschk]

Ok.. I found in RM0468 text (and figure 162)

> clock divider factor of 2 is applied to the clock provided to the ADC analog

block (fadc_ker_ck).

Does fADC in datasheet mean fadc_ker_ck or fadc_ker_ck_input?? CubeMX seems to check the limitation at fadc_ker_ck_input

[Kolja Waschk]

Datasheet says "fADC refers to fadc_ker_ck" for 12-bit ADC, but nothing about 16-bit-ADC

[TDK]

fADC refers to fadc_ker_ck for all ADCs.

I'm able to set ADC input clock to 100MHz in CubeMX, which would give 50 MHz after the divider. Is that what you're trying to do?

[Kolja Waschk]

I have configured ADC Clock Mux to output slightly more than 126,5 MHz from PLL2P.

In ADC_Settings for ADC1 my choices are limited to "Asynchronous clock mode divided by 4" and higher, ie. max 126.5 MHz/4 = 31.625 MHz, then further divided by 2 yields only 15.812 MHz.

When hovering over "Asynchronous clock mode divided by 2", a popup text says "Prescaler divider not respecting Fadc Min Max Constraint" .. but 31,625 MHz wouldn't exceed 50 Mhz?!

[Kolja Waschk]

(sorry typo 15 Hz => 15 MHz)

[TDK]

Ensure you're in VOS0 in RCC -> Power Regulator Voltage Scale. If that's not it attach your IOC.

You can go back and edit your post to correct typos.

[Kolja Waschk]

Ah! That dependency is new to me. After changing current setting (VOS1) to VOS0, smaller divisors and thus higher clocks can be chosen.

Can you help me to locate the relevant documentation about the limitation on the Fadc or due to voltage scaling? Until now I just found the reference manual "Maximum allowed frequency" in table 56 where it shows a max of 160 MHz (with VOS0 and VOS1) for clock to ADC, and the datasheet just seems to state that Fadc max of 16-Bit ADC is 50 MHz.

Thanks for the insights!

Kolja

[TDK]

In the reference manual, "Table 56. Kernel clock distribution overview"

[Kolja Waschk]

I currently have configured VOS1. Table 56 shows 160 Mhz limit with VOS1. How is this related to the limitation on Fadc that I experience? I get 126,5 MHz from PLL2P (which is below 160) and I'm not allowed to feed this divided only by 2 into f_adc_ker_ck_input, which (after another division by 2) would result in 31,5 MHz f_adc_ker_ck (which is below 160 and below 50). So there's still something I do not understand... Sorry...