STM32H5E4 PLL3 VCI Range incorrect from CubeMX
I’m working on a new project based on the STM32H5E4, and hit a weird problem, that smells like a CubeMX bug, with PLL3 init.
Seems CubeMX is putting out incorrect values for the VCI Range (PLL3RGE bits in the init structure), relative to the comments in the H5 HAL RCCEX header.
I’ve got a 12MHz HSE, divided by 3 [PLL3M] for 4MHz, then multiplied by 48 [PLL3N] in the PLL for 192MHz, then divided by 4 [PLL3Q] for 48MHz for the USB 48MHz clock.
Here’s it’s generated code:
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_OTGFS;
PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE;
PeriphClkInitStruct.PLL3.PLL3M = 3;
PeriphClkInitStruct.PLL3.PLL3N = 48;
PeriphClkInitStruct.PLL3.PLL3P = 2;
PeriphClkInitStruct.PLL3.PLL3Q = 4;
PeriphClkInitStruct.PLL3.PLL3R = 2;
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_0;
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_MEDIUM;
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
PeriphClkInitStruct.OtgfsClockSelection = RCC_OTGFSCLKSOURCE_PLL3Q;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
I’d expect VCI Range 1 (2-4MHz) or Range 2 (4-8) but getting VCI Range 0 (1-2MHz).
I’ve tried different combinations of dividers / multiplers (to get the same 48MHz output) and it doesn’t ever seem to get it right.
It looks like it’s selecting the VCO Range correctly - This went to the higher range when I expected it to, given other settings.
Also toyed with PLL1, and it seems unaffected.
I’ve added code in the user section in HAL_PCD_MspInit below to fix this:
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_OTGFS;
PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE;
PeriphClkInitStruct.PLL3.PLL3M = 3;
PeriphClkInitStruct.PLL3.PLL3N = 48;
PeriphClkInitStruct.PLL3.PLL3P = 2;
PeriphClkInitStruct.PLL3.PLL3Q = 4;
PeriphClkInitStruct.PLL3.PLL3R = 2;
PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_2; /* 4 MHz ref: 4-8 MHz band */
PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; /* 192 MHz VCO */
PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ;
PeriphClkInitStruct.OtgfsClockSelection = RCC_OTGFSCLKSOURCE_PLL3Q;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
Can anyone confirm similar results?
