SCB_CleanDCache_by_Addr needs to accept an address not 32 byte aligned.

[Thomas E.]

The function SCB_CleanDCache_by_Addr needs to be able to handle address that are not 32 byte aligned, but expanding the data cache flushing region to conforming addresses that included the requested region.

netXduo calls the function regardless of regions and does not expand the region to the 32 byte alignment.

Thus current our mitigation is completely turn off data caching on the part.

STM please fix. As of 2021.10.23 using the latest H7 pack and STM32cubeMX.

[TDK]

> The function SCB_CleanDCache_by_Addr needs to be able to handle address that are not 32 byte aligned

Blindly expanding the region so it matches a 32-byte boundary will introduce other problems. The array itself needs to be aligned and a multiple of 32-bytes. This is not something that can be solved within the SCB_CleanDCache_by_Addr function.

[Piranha]

Those functions were fixed (implementing the address and size expansion) by ARM long ago:

https://github.com/ARM-software/CMSIS_5/commit/ab35be31712f978b8b031d6438ea180c107cf171

Just check/update the CMSIS core related include files. ST is terribly slow in updating anything, but the current version is correct.

https://github.com/STMicroelectronics/STM32CubeH7/blob/5975bffae9358bc2b2890a35a203d940a395efef/Drivers/CMSIS/Include/core_cm7.h#L2542

As TDK said, it doesn't magically solve all cache related problems. For proper usage of those functions, read my post here:

https://community.st.com/s/question/0D53W00000oXSzySAG/different-cache-behavior-between-stm32h7-and-stm32f7

[Pavel A.]

Well then a bug should be filed against NetX?