Potential bug in CubeMX for H733VGT6 with OCTO SPI?

[Southbranch]

Hi,

I am trying to configure multiplexed OCTO SPI for the above MCU.

Only Chip Select Port 1 NCS comes up as an alterantive for OCTOSPI1, and for OCTOSPI2 the Chip Select Port is is disabled, I would have expected Port 2 NCS to come up here... 

Is this a bug or am I missing something?

 

 

 

 

[Imen.D]

Hello @Southbranch,

OCTOSPI2 is enabled if Port1 NCS is selected in OCTOSPI1.

But you won't be able to select Chip Select Port1 NCS in OCTOSPI2 since it is already selected in OCTOSPI1. This is caused by the fact that Port2 is not available with the package.

To further clarify, when using direct mode, only one instance of OCTOSPI will be enabled, the other one will be disabled since in direct mode, using 2 OCTOSPI instances means that each instance will be on a different Port and in this case we have only one Port: Port1 ==> Only one instance can be enabled in direct mode.

When using multiplexed mode, we can enable both instances of OCTOSPI since they will be on the same Port, in this case Port1. So, for NCS signal, it will be enabled in one of the instances (not both).

[Southbranch]

 

Hi Imen and thanks for your reply,

However, I am struggling following you.

I have previously been using multiplexed mode for an Infineon OCTO SPI multichip chip (Ram + Flash) with the STM32H725IGK6 on a custom board, however, I have now realized I won’t be needing all the pins on that package and thus I was looking for a simpler package.

But I can't see how I could use multiplexed mode without using both NCS 1 + 2 since my mem-chip have separate pins CS1 for flash and CS2 for Ram?

[Imen.D]

Hi @Southbranch,
STM32H733VGx (LQFP100 and TFBGA100 packages) cannot have the TWO OctoSPI at the same time on two different memory because 2_NCS is not available.

The OCTOSPIM enables a multiplexed mode where OCTOSPI1 and OCTOSPI2 controllers share dynamically a single physical port.
This is useful for instance to support one SPI_NOR and one SPI_NAND devices attached to the same port and controlled by independent OCTOSPI controllers.
==> When working with multiplexed mode, there is no need for 2 ports, only one port is sufficient.

[Southbranch]

Hi Imen,

Thanks for getting back.

"==> When working with multiplexed mode, there is no need for 2 ports, only one port is sufficient."

Yes I understand, only one dataport is needed which is the whole idea, but two NCS (Port 1+2) are needed, or have I missed something trivial? Picture to the right below.

A long shot, but what about connecting NCS1 to CS1 and then connecting a logical inverter to CS2 via NCS1? In that case, when NCS1/CS1 goes low CS2 automatically goes high and vice versa. In theory it would then give access to both memories in multiplexed mode using only NCS1.

I am about to move on to another MCU, so any last comments are highly appreciated

 

 

[Imen.D]

Hi @Southbranch,

You are right and your understand is correct.

"no need for 2 ports, only one port is sufficient." => I mean only one data port. But we need two NCS: CS for port 1 and CS for port 2 as explained in the below figure from AN5050:

So, Multiplexed mode requires BOTH: OCTOSPIM_P2_NCS and OCTOSPIM_P1_NCS

as mentioned in the RM0468:

OCTOSPIn_NCS are not part of the multiplexing. Only OCTOSPIn_IOs, OCTOSPIn_DQS and OCTOSPIn_CLK / OCTOSPIn_NCLK are multiplexed.

Hope this answer your question.

If you still have issues, please don't hesitate to come back to the Community.