PLL input frequency DATASHEET versus CUBEMX

[GChat.1]

Hello,

I have found a difference between the PLL input frequency specification between the datasheet of the L4S5 :

And CUBEMX data :

Datasheet limit is at 16MHz, CUBEMX limit is at 8MHz.

Is there any errata sheet tht specify this difference?

Thank you for your answer,

Sincerely,

Guillaume

[Imen.D]

Hello @GChat.1​ ,

I will forward this issue internally to check, then will come back to you with update.

Best Regards,

Imen

[Imen.D]

Hello @GChat.1​ ,

After check, according to the datasheet :

"- 4 to 48 MHz high-speed external crystal or ceramic resonator (HSE), that can supply a PLL.

The HSE can also be configured in bypass mode for an external clock.

- 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can supply a PLL

...

"

The PLL input frequency can be used :

• HSE : MAX frequency is 48
• HSI : Max Frequency is 16

and it's the case using CubeMX.

The Default value in the Clock config Panel - Input Frequency is 8MHz, but it can reach 48MHz (you need just to enable the RCC HSE).

Best Regards,

Imen

[Tesla DeLorean]

Certainly in prior designs the HSI was a pulse generator, so not 50/50 duty, and thus needed a flip-flop to divide by 2 and give a clean 50/50 clock source.

The PLL's VCO is very much a rapid pulse generator, again the reason the PLL clocks needing a DIV2, DIV4, etc on the output as the core needs a 50/50 clock as it uses both phases.

[GChat.1]

Thank you for your feedback,

My question is more simple :

Why CUBEMX returns an error when I set a PLL input frequency greater than 8MHz as the input limit indicated in the datasheet page 165 is :

" fpll_in min : 2,0645 MHz ; fpll_in max : 16MHz"

Thank you for your new feedback,

Sincerely,

Guillaume