How to map OCTOSPIM to port G on STM32U5Axxx

[MikeStrom]

I'm new to STM32CubeMX and have difficulties finding out how to map all OCTOSPIM_P2 signals to Port G. I can manually map some signals to Port G (CS, IO[7:4], DQS), but can't figure out how to map the rest. 

 

Any help most welcome!

[KDJEM.1]

Hello @MikeStrom,

 

I recommend you to refer to the STM32U5A datasheet and precisely Table 27. STM32U5Axxx pin/ball definitions and check whether you are able to map all OCTOSPIM signals to port G or not??

For example,  OCTOSPIM_P1_CLK signal is not available on port G.

Also you can used search method to find the availability of signal on different pins as shown in the below figure

 

I hope this help you.

Thank you.

Kaouthar

 

 

[MikeStrom]

Thanks for the feedback @KDJEM.1

It appears that it is not possible when reading Table 27. However, that means that the text in para 3.28 is a bit misleading:

Since we consequently are forced to run the entire CPU on 1V8, is it correct that we can run the OSPI clock at 93MHz in both SDR and DDR mode, effectively reaching 93MT/s and 186MT/s with 8 lanes? It looks possible to me from the data sheet, but I might have overlooked something. 

Thanks!

[Tesla DeLorean]

>>effectively reaching 93MT/s and 186MT/s with 8 lanes?

Some how I think that's probably super optimistic, and ignores achievable burst lengths, overhead and latency.

In OCTOSPIM nomenclature I think full I/O matrix means mapping of high/low banking. Perhaps allowing for interchange of CLK, NCS, DQS, IO's from P1 to/from P2

Although I don't see a OCTOSPIM CLK for either bank on GPIO-G

Can VCCIO be 3V3 if the rest of the MCU is at 1V8 ?