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arilink
Associate III
Oct 14, 2021 5:51 AM UTC
Solved

How many endpoints does STM32F105RBT6 USB have?

The STM32F105RBT6 manual shows that there are 1 control endpoint, 3 IN endpoints, 3 OUT endpoints, but the USB driver code generated by CubeMX now shows hpcd_USB_OTG_FS.Init.dev_endpoints = 4; are these 3 IN and OUT endpoints shared? 4 endpoints and 1 is the control endpoint for user-defined use, only 3 are not enough and they are less than the lower-end STM32F1030693W00000FCSvnQAH.png

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Khouloud OTHMAN
Khouloud OTHMANBest answer
Associate
Oct 19, 2021 4:46 PM UTC

Hello @arilink​ ,

First let me thank you for your feedback.

In fact, each USB has 1 control end point + x IN EPs + OUT EPs (IN and OUT endpoints are always equal) then the generated value must be x+1.

Thus, dev_endpoints value is correctly generated by CubeMX: hpcd_USB_OTG_FS.Init.dev_endpoints = 4.

Furthermore, backing to STM32F105xx, STM32F107xx, STM32F2xx and STM32F4xx USB On-The-Go host and device library User Manual > OTG_FS interface main features, the  OTG_FS interface has four bidirectional endpoints, including 1 control endpoint and 3 device endpoints which support bulk, interrupt and isochronous transfers.

Hope this answers your question, if this this case, please click on the Select as Best button on my reply . This will help other members of the community find this solution more quickly.

Khouloud.

5 replies

Khouloud OTHMAN
Khouloud OTHMANBest answer
Associate
Oct 19, 2021 4:46 PM UTC

Hello @arilink​ ,

First let me thank you for your feedback.

In fact, each USB has 1 control end point + x IN EPs + OUT EPs (IN and OUT endpoints are always equal) then the generated value must be x+1.

Thus, dev_endpoints value is correctly generated by CubeMX: hpcd_USB_OTG_FS.Init.dev_endpoints = 4.

Furthermore, backing to STM32F105xx, STM32F107xx, STM32F2xx and STM32F4xx USB On-The-Go host and device library User Manual > OTG_FS interface main features, the  OTG_FS interface has four bidirectional endpoints, including 1 control endpoint and 3 device endpoints which support bulk, interrupt and isochronous transfers.

Hope this answers your question, if this this case, please click on the Select as Best button on my reply . This will help other members of the community find this solution more quickly.

Khouloud.

arilink
arilinkAuthor
Associate III
Oct 21, 2021 1:45 AM UTC

I see. Thank you very much for your answers

waclawek.jan
Super User
Oct 19, 2021 7:37 PM UTC

> only 3 are not enough

Whatever the number is, it's never enough for all possible use modes.

> and they are less than the lower-end STM32F103

The 'F103 has an entirely different USB module, device only, whereas the 'F105/107/'F2/'F4/'F7 and the upper-end 'L4 have device-host-OTG module (of which 'F2/'F4/'F7 have two), with number of endpoints changing from model to model.

JW

arilink
arilinkAuthor
Associate III
Oct 21, 2021 1:47 AM UTC

I don’t understand why the number of endpoints of high-end models is less than that of low-end models, and 4 endpoints are not enough for USB composite devices.

waclawek.jan
Super User
Oct 21, 2021 7:49 AM UTC

The OTG module is much more complex and probably consumers more silicon space per endpoint.

At the end of the day, why would it matter - just take it as a fact and move on. If 2x3+control EP won't suit your application, choose a different STM32 model (or any other solution out there).

JW