Hi, for part number STM32F746NG, in STcube, while configuring the pins SDRAM is showing warning sign. In conflict definition, it is showing conflict with its own pins. Configuration is: LCD RGB888, SDRAM, QSPI, 2 I2C, UART, I2S, JTAG.

[SKuma.26]

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[Khouloud ZEMMELI]

Hi @Community member​ 

Can you please share your ioc file to check the conflict message?

Thanks, Khouloud

[SKuma.26]

Hi @Khouloud ZEMMELI​ , thank you for quick response.

Please refer attached .ioc file.

Regards,

Sunney

[Khouloud ZEMMELI]

Hi @Community member​ 

Thanks for sharing your project.

Actually, there's a warning note on CubeMX which present the conflict on SDMMC MMC 8 bits Wide bus mode with QuadSPI or/and UART4 or/and I2C or/and LTDC, the reason of this conflict is that these IPs ( in some specific modes ) share the same pins (PB8, PB9, PC6/8/9/10/11/12 and PD2) which are needed for some signals used when MMC 8 bits mode is Selected.

Let's start with the UART4 Asynchronous : here, the shared pin is PC10 which is assigned to UART4_TX (there's an alternate pin : PA0/WKUP), same for the LTDC RGB888 (24bits) : PB9 assigned to LTDC_B7 (there's 2 alternates pins : PJ14 and PG10) and PD2 assigned to LTDC_B2 (there's 2 altenates pins : PK6 and PI7), So they can be used with MMC 8 bits mode.

For case of I2C : PB8 assigned to I2C_SCL (there's an alternate pin : PB6), so there's no problem to use it with MMC 8 bits mode.

Now, if you want to use the QuadSPI Bank1 which assign PC9 to QUADSPI_BK1_IO0, and as there's an alternate pin PD11, so normally it's ok to use it with MMC 8 bits mode , but not with the I2C.

In fact, the PB6 is needed to the QUADSPI_BK1_NCS signal ( there's no alternate pin for this signal ) and at the same time it's is assigned to I2C_SCL instead of PB8, and this explains the disappearance of the warning on SDMMC when deactivating one of the two IPS (QuadSPI single Bank and I2C).

Hope my answer helped you to understand the reason of the warning, when your question is answered, please close this topic by choosing Select as Best. This will help other users find that answer faster.

Always welcome, Khouloud

[SKuma.26]

Hi @Khouloud ZEMMELI​ ,

Yes, in MMC case explanation holds good. Please see the below screen shot for the warning note on FMC (SDRAM2) where it shows conflict with Clock and Chip enable of its own.

  

Regards,

Sunney

[Khouloud ZEMMELI]

Hi again @Community member​ 

For the case of FMC, for each SDRAM you have the possibility to choose one of two modes: SDCKE0+SDNE0 and SDCKE1+SDNE1, if one mode is selected for SDRAM1 so you can select only the other mode for SDRAM2 ( automatically the mode selected for SDRAM1 becomes grayed on SDRAM2 ).

To conclude, this warning is here just to inform you that you cannot select the SDCKE0+SDNE0 mode on SDRAM1 since it is used with SDRAM2, otherwise, there's no problem with your FMC configuration.

Thanks for your contribution, Khouloud