FIFO configuration for U(S)ART instances of STM32L4R5

[WTayl]

The reference manual (RM0432) for the STM32L4R5 shows that UART4 & UART5 support two 8-byte FIFOs. I can't figure out how to configure the IRQ level thresholds. CubeMX shows levels for LPUART1 and USART1/2/3, but not UART4/5.

"Table 264. USART/LPUART features" shows that LPUART1, USART1/2/3 and UART4/5 all support Tx/Rx FIFO and that the Tx/Rx FIFO size (in bytes) is 8.

[Amel NASRI]

Hello,

Based on RM0432, "The USART comes with a Transmit FIFO (TXFIFO) and a Receive FIFO (RXFIFO). The FIFO mode is enabled by setting FIFOEN in USART_CR1 register (bit 29). This mode is supported only in UART, SPI and Smartcard modes."

So, I agree with you that UARTs support FIFOs.

Both UARTs and USARTs configuration related to FIFO should be reviewed in STM32CubeMX. This is tracked internally.

-Amel

[WTayl]

STM32CubeMx does not allow for configuring FIFO level interrupt. Is this a bug in STM32CubeMX?

[Amel NASRI]

Yes, it should be a bug and as already said, it is tracked internally to be fixed in coming releases of STM32CubeMX.

[Khouloud ZEMMELI]

​Hello @Community member​ 

the fix will be available in the next release.

Best Regards,

Khouloud.

[Amel NASRI]

Hello,

CubeMX 5.5 is already available; the issue should be already fixed with this version.

-Amel

[WTayl]

Thanks! I will give it a look