Cube32MX_IDE and STM32L562VET6Q FMC does not support SRAM, nor properly support LCD memory mapped controller. Data sheet says yes, FMC mode in IDE says no. Which is right?

[Harvey White]

Working on a hardware design for the STM32L562VET6Q (because that's all that's left with enough memory!)

Want to add an S1D13517 (Epson) display controller. Said controller is memory mapped, 16 data bits, needs CS, etc, and one address line to select register/data (indirect memory mode). FMC on F767 supports this under LCD. L5 has FMC and LCD mode, but apparently only allows multiplexed connections (A16 is first address line available.) This is consistent with multplexed SRAM (which may be all this chip can do).

However, the data sheet says it does straight SRAM, and CubeMX says it doesn't (and doesn't give me the support software).

Which is correct?

The limitation of non multiplexed SRAM not supported seems odd, but it could be a pin limitation in the LQFP-100 chip. However, didn't see anything about that in the data sheet.

What's the answer?

[Harvey White]

Well, just found the answer in the fine print in the datasheet.

The LQFP-100 package has a crippled FMC controller that only supports Multiplexed PSRAM and NOR. Now the question becomes, if I the A16 line (since A0 to A15 are multiplexed), and I use it for register select, is this a valid way for it to work? Documentation on how to use the FMC in LCD mode is absent (although I do know how the F767 works). In this case, will the L5 chip behave properly?