Why duty cycle of I2C not 50% ?

[noobmaster69]

Hi. I am using STM32L031 for my project. And I am using I2C to read eeprom. It is reading eeprom properly but if you see duty cycle on SCL(red one in the pic below), it is not 50%.

My I2C spped is 400kHz. ON time I get is 750ns and OFF time is 1.96us. Why is this happening?

(NOTE: I have nRF52833 connected to the same eeprom as well)

I used STM32CubeIDE to generate code.

[Tesla DeLorean]

The I2C timing parameter is rather complex and involved, and uses the APB clock to control the widths,rise/fall time, etc.

You can likely tune it to suit your needs/expectations, along with stretching options.

[Andrew Neil]

@Community member​  "duty cycle of I2C not 50%"

Should it be?

Surely, I2C is concerned with edges & levels - not widths?

(apart from minimum requirements)

I don't think the I2C specification requires it?

https://www.nxp.com/docs/en/user-guide/UM10204.pdf

Does the STM32 documentation suggest that it should be?

[Harvey White]

I seem to remember that at 100 Khz, the clock and such are closer to 50%. At the 400 Khz mark, the clock is not specified to be symmetric. It may have to do with bus propagation delays, but it is not, IIRC, a 50% duty cycle. You might want to look at other peripheral chips and examine the typical waveforms for various clock speeds. Going to 1.5 Mhz (if available) is even stranger, I think.