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RadiantBadger
Visitor II
February 12, 2026
Question

STM32N6 CoreMark with GCC

  • February 12, 2026
  • 1 reply
  • 469 views

Hello ST Community!

I am currently considering an STM32N6 for a new project and decided to use CoreMark as one of the benchmarks to compare candidates. According to its datasheet and published results on https://www.eembc.org/viewer/?benchmark_seq=13733, the STM32N657 should reach a score of ~3616. I noticed that the published results on the EEMBC website report usage of “ArmClang v15.0 - Keil v6.18” as the compiler. I figured it would be worthwhile checking what score I’d get from STM32CubeIDE’s GCC toolchain.

I ran the test on a NUCLEO-N657X0-Q board and obtained a CoreMark score of 2389, which is quite a bit lower than I expected when comparing against the published results.

The test application is designed as follows:

  • CoreMark source code from https://github.com/eembc/coremark using the instructions in barebones_porting.md.
  • CPU clocked at 800 MHz.
  • Overdrive voltage obtained from external power supply (Pin PB12 = 1).
  • Code runs from ITCM.
  • Data and Stack are placed in DTCM.
  • Interrupts and SysTick timer are disabled during the CoreMark test execution.
  • Optimization set to -Ofast.

I confirmed that my timer (TIM2 configured at 100 MHz) and CPU clock frequency are correct using external equipment and the CM55’s DWT cycle counter.

I also tried:

  • Enabling Link-Time Optimization by adding -flto to compiler and linker options.
  • Leaving the code in the SRAM and enabling cache.

But neither of those gave a better result than the initial configuration.

Are there CoreMark test scores available with ST’s own toolchain that I could compare with?

Is the “ArmClang v15.0 - Keil v6.18” toolchain really that much better than GCC at producing executable object code for the CoreMark test that it explains that large of a gap in test score?

Any additional suggestions on what should be configured to reach maximum performance?

Thanks!

1 reply

wilson234
Visitor II
July 29, 2026

I was interested to see these GCC results because the test setup appears to follow most of the recommended CoreMark practices, ITCM/DTCM placement, 800 MHz operation, disabled interrupts, and -Ofast. A ~34% gap compared to the published ArmClang/Keil score does seem larger than expected, but compiler choice alone can make a noticeable difference on Cortex-M55 due to instruction scheduling and optimization strategies. It would be interesting if ST could share a reference CoreMark project built with STM32CubeIDE/GCC, along with the exact compiler version and flags they recommend. That would help determine whether the remaining gap comes from the toolchain itself or from subtle configuration differences in the benchmark setup.👍

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