STM32L412 External Crystal RTC inaccuracy of 24-30 Seconds in 24 Hours

[DBhut.1]

Hello,

We are using STM32L412 RTC with STM32CubeIDE.

Previously we are using

Crystal - 32.768 Khz SMD Crystal YXC YSX306GA 8.0 x 3.8 mm

load capacitance - 10pf 0805

In Previous Crystal we get about 6 seconds of RTC drift,

to solve this issue, study the application note AN2867 : https://www.st.com/resource/en/application_note/cd00221665-oscillator-design-guide-for-stm8afals-stm32-mcus-and-mpus-stmicroelectronics.pdf

and from this used below setup:

Crytsal - ABRACON ABS25-32.768KHZ-6-T Crystal, 32.768 kHz, SMD, 8mm x 3.8mm, 20 ppm

load capacitance - 6pF 0805

But In new setup we are getting 24-30 seconds of drifiting.

As we are following all guidlines mention in application notes, as compared to previous crystal, but getting more rtc drift (almost 4 time of previous rtc drift)

Please help us to solve this issue.

Thank You

[Peter BENSCH]

The deviation (6s/d -> 69ppm, 24...30s/d -> 278...347ppm) is much too large for normal crystals, so the causes must be found.

How did you set up your clock tree?

What does your layout at and around LSE look like?

Are there any tracks with switching edges near the LSE components?

Regards

/Peter

[DBhut.1]

No Switching Edge Component near crystal

 

 

Schematic for crystal:

 

PCB Layout:

 

no component or tracks below XTAL on bottom of PCB

[DBhut.1]

Hello @Peter BENSCH​ , I have some doubt about crystal connections:

 

As shown in above schematic, crystal pins 1 and 4 is quartz crystal and another two pin (2 and 3) is connected to GND.

In many schematic, we found that some schematic keep crystal other pin floating.

and according to crystal datasheet: https://abracon.com/Resonators/abs25.pdf

 

Pin 2 and 3 are not Connected to GND (Floating).

So,

1) Is above schematic is ok?

2) What can be impact with GND Connection to pin 2 and 3?

3) What can be impact without GND Connection to pin 2 and 3?

[Peter BENSCH]

Well, first of all, the clock scheme looks ok.

You have connected the crystal using very short tracks to the STM32L412C, but GND looks very suspicious: no GND area under the crystal, no guard ring around crystal and its C's, no shortest possible connection from GND (crystal, C's) to the GND of the STM32L412C.

I always have a standard statement for this:

But please don't forget to layout GND accordingly, i.e. shaped like a (GND) hand holding a stone (crystal), where the "hand" must be separated from the rest of the GND layer and only connected via the "arm" to the closest GND pin of the STM32, see AN2867, section 7.2, fig. 14...16. I hope that the linguistic picture illustrates this in an understandable way?

Unfortunately, we don't see where GND is routed from the crystal + C's to the STM32 in your case, nor do we know the circuit, so we can't rule out the possibility that interference pulses are interspersed somewhere that lead to the observed deviation.

Regards

/Peter

[waclawek.jan]

As an experiment to confirm Peter's suspicion, try to mount C63/C65 "upright" so that only the crystal-connected terminal is soldered down, and then using shortest possible wires connect their "upper" other ends to the ground terminal of C62.

You may also try to mount the crystal a bit slanted so that its ground terminals are not connected to the pads, and connect those terminals to the same ground as the two crystals [EDIT see Peter's comment below] capacitors [/EDIT]

JW

[DBhut.1]

I have performed this testing, and rtc drift in 24 hours is about 20 seconds(earlier 24 seconds) and still device is in testing.

[Peter BENSCH]

Thanks Jan, but in your last sentence you probbly meant "...and connect those (crystal) terminals to the same ground as the two crystals capacitors."

/Peter

[DBhut.1]

 

This is bottom and top view of PCB.

Due to size and placement issues, we can't use crystal guard rings, and Crystal GND direct connection to MCU GND is not possible, it is done through via's (Shown in Green Circle).

Please review this.

[waclawek.jan]

LSE oscillator is ultra low power, so any small disturbance can influence it. That's why it's important that it does not share ground with any other circuitry on the board: any current flowing together with the LSE current can influence LSE.

You also can try to play with RCC_BDCR.LSEDRV, but I would recommend you to make the experiment I outlined above first.

JW

[LCE]

Just to make sure:

there are only TOP and BOTTOM layers, no mid-layer(s) with an unbroken GND-plane?

If there's a GND plane and not much switching / power stuff going on in the vicinity of the crystal, it should be okay.

But, if there is no GND plane, then send the person who did the PCB layout back to school. ;)

A 4-layer PCB these days doesn't cost much, and with 2 layers it might be quite hard to do a good layout with sensitive components and high speed / power stuff.

[DBhut.1]

this is 2 layer PCB

[LCE]

Ouch...

Then the GND connection between STM32 and not only the crystal, but most other components is... terrible.

Always think of GND as a signal.

It doesn't help if you get short "signal" traces between 2 devices, but the GND connection between them is taking "a long way".

Even worse, because GND is kinda "shared connection".

[Oliver Sedlacek]

When you say 24 secs of drift, do you mean a fixed (give or take) error, a difference with temperature or random errors over 24 hours. Can you route the LSE output to an MCO to a pin so you look at it cycle by cycle.

Is the stability affected by drive power level?