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July 22, 2026
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STM32F777 impossible to move data to SRAM1

  • July 22, 2026
  • 6 replies
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Hello everyone.

I will use my MCU to acquire big amounts of analog data and transfer them to a host using UDP.

As DTCM is 128K and SRAM1 is 368K I would like to store those data in SRAM1. As an exercice I’m trying to configure LwIP in SRAM1.

I’ve followed many tutorials (MPU is, I beleive, set correctly) :

with a cache protected region where all the LwIP data should be (normally it should only matter when I’ll run this program) 

I’ve also configure ETH to point to this area :

And Lwip is also configured with this same area

And the flash script is also set :

But when I compile the code directly after importing from cubeMX, I get :

Data are not in SRAM1, they are in the DTCM.

Am I missing something ? Do I have to set some options in the compiler ?

Also I’m a bit surprised to see that 4 descriptors x 32 bits = 0xa0 (0d160) ??? Or F777 descriptors are 40 bits ?

Thanks to anyone who will take some time to help me.

Best regards

 

Best answer by mƎALLEm

 

Is it OK to do such thing :

 

It looks good in the Memory Details tab :

 

Yes it’s OK

 

No issue to put heap and stack anywhere in the internal RAM including SRAM2. The CPU is accessing all the memory resources in the product. For performance reasons, need to activate the cache for that region (heap and stack): enable the cache and ensure SRAM2 is cacheable with MPU.

 

 

6 replies

mƎALLEm
ST Technical Moderator
July 22, 2026

Hello ​@Haarkon and welcome to the ST community,

What is the definition of RAM here:

  } >RAM

What’s the origin defined in the linker file? in the DTCM or in the SRAM1?

For example from this example  this is how it was implemented in the linker file:

MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 499K
Memory_B1(xrw) : ORIGIN = 0x2007C000, LENGTH = 0xA0
Memory_B2(xrw) : ORIGIN = 0x2007C0A0, LENGTH = 0xA0
}

Then: 

  .ARM.attributes 0 : { *(.ARM.attributes) }
.RxDecripSection (NOLOAD) : { *(.RxDescripSection) } >Memory_B1
.TxDescripSection (NOLOAD) : { *(.DMATxDscrTab_section) } >Memory_B2

 

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HaarkonAuthor
Associate
July 23, 2026

Hello ​@Haarkon and welcome to the ST community,

What is the definition of RAM here:

  } >RAM

What’s the origin defined in the linker file? in the DTCM or in the SRAM1?

For example from this example  this is how it was implemented in the linker file:

MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 499K
Memory_B1(xrw) : ORIGIN = 0x2007C000, LENGTH = 0xA0
Memory_B2(xrw) : ORIGIN = 0x2007C0A0, LENGTH = 0xA0
}

Then: 

  .ARM.attributes 0 : { *(.ARM.attributes) }
.RxDecripSection (NOLOAD) : { *(.RxDescripSection) } >Memory_B1
.TxDescripSection (NOLOAD) : { *(.DMATxDscrTab_section) } >Memory_B2

 

The RAM (and FLASH) definition are the one that CubeMX/Cube IDE produce :

It’s OK, as memories DTCM, SRAM1 and SRAM2 are abutting

 

Is it OK to do such thing :

 

It looks good in the Memory Details tab :

I believe that in this case, my stack and my heap are now in the RAM section and no longer in SRAM2 ?

Is it OK to move the Heap and the stack, back in SRAM2 using 

One more time thank you.

mƎALLEm
mƎALLEmBest answer
ST Technical Moderator
July 23, 2026

 

Is it OK to do such thing :

 

It looks good in the Memory Details tab :

 

Yes it’s OK

 

No issue to put heap and stack anywhere in the internal RAM including SRAM2. The CPU is accessing all the memory resources in the product. For performance reasons, need to activate the cache for that region (heap and stack): enable the cache and ensure SRAM2 is cacheable with MPU.

 

 

To give better visibility on the answered topics, please click "Best answer" on the reply which solved your issue or answered your question.
TDK
July 22, 2026

“. = ABSOLUTE(...)” doesn’t do what you want it to. It looks to be a vibe coded suggestion. Creating two linker sections and placing the variables there will work.

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HaarkonAuthor
Associate
July 23, 2026

Thanks for your answers. it works !

I’ve got one last question : Can those memories overlap themselves ?

Best regards

mƎALLEm
ST Technical Moderator
July 23, 2026

Hello,

If your question has been answerd please mark as Best Answer the post that provided you the solution (not this one).

New question = new post. There, please tell what do you mean by “overlap themselves”? in software or by hardware ?

To give better visibility on the answered topics, please click "Best answer" on the reply which solved your issue or answered your question.