STM32 RCC Configuration with Register

[AÜNAL.1]

Hi,

I am using STM32F407 discoveryboard and I am trying to set the RCC configuration such as the clock frequency is 168 MHz. I configure the register as I want but some bits at the RCC_PLLCFGR registers are already assigned to 1, and when I cleared these bits, the code wasn't work. I am adding the code below(I am using STM32CubeIDE) Could you help me please?

#define PLL_M 8

#define PLL_N 336

#define PLL_P 0 // PLLP = 2

extern uint32_t SystemCoreClock;

uint32_t systemClock;

void RCC_Config(void){

RCC->CR |= (1 << 16); // HSE On

while(!(RCC->CR & RCC_CR_HSERDY)); // Wait HSE Active

RCC->CR |= (1 << 19); // CSS On

RCC->PLLCFGR |= (1 << 22);  // PLL Source is HSE

RCC->PLLCFGR |= (4 << 0);  // PLL_M : 4

RCC->PLLCFGR |= (168 << 6); // PLL_N : 168

RCC->CR |= (1 << 24);     // PLL is on

while(!(RCC->CR & (1 << 25))); // Wait PLL Ready

RCC->CFGR &= ~(1 << 0);   // To set PLL, Bits(1:0) must be 10, so 0th bit is configured as 0

RCC->CFGR |= (1 << 1);   // PLL selected as system clock

while(!(RCC->CFGR & (1 << 1))); // Select system clock is PLL

RCC->CIR |= RCC_CIR_HSERDYC;

RCC->CIR |= RCC_CIR_CSSC;

}

int main(void)

{

RCC_Config();

SystemCoreClockUpdate();

systemClock=SystemCoreClock;

while (1)

{

}

}

[TDK]

Probably not the answer you want, but you can step through how HAL updates the registers and copy that, or at the very least compare register values at the end of HAL initialization to what you're doing. Likely you are missing some detail. I scanned but didn't spot anything.

Note that the default value of PLLCFGR is not zero. Perhaps that assumption is causing some issues.

[Piranha]

As TDK already said, you are doing an OR between the default RCC_PLLCFGR value and your desired value. Also you are not adjusting the FLASH latency and APB bus dividers before rising the SYSCLK frequency.

And use the provided register bit field defines for all bits, not just some.