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oeliks
Associate III
January 22, 2024
Solved

GPIO alternate write acces? SPI CLK

  • January 22, 2024
  • 8 replies
  • 5311 views

Hi! Do we have write acces on pin set to alternate function push-pull?

 

Problem: CLK line floats after hal_transmitreceive, pullup helps but distorts clk line.

And with pullup there seems to be a glitch at end that slave can detect as fake clock cycle and push MSB out of its scope and add to end radom bit.

Should i go with LL spi will this help?

Attachment: clk with pull-up, yellow - clk

SDS00012.png

    This topic has been closed for replies.
    Best answer by Pavel A.

    Yes exactly. Enable Master Keep IO state.

    8 replies

    TDK
    January 22, 2024

    CLK line should stay driven as long as the peripheral is enabled. Which chip? Show code.

    "If you feel a post has answered your question, please click ""Accept as Solution""."
    oeliks
    oeliksAuthor
    Associate III
    January 22, 2024

    STM32H723 (genuine)

    CubeIDE 1.14.1

     

    Will post code tomorrow (I'm on night shift at the moment).

    Do You want me to find and post here some specific part of code?

    Pavel A.
    January 22, 2024

    Which STM32? Some models have a setting that releases SPI pins after a transaction. If this is your case, disable releasing the pins.

    oeliks
    oeliksAuthor
    Associate III
    January 22, 2024

    Its STM32H723ZG

     

    Przechwycenie obrazu ekranu_2024-01-22_20-29-49.png

    How to disable releasing the pins?

    Master keep io state : enable ?

    Or should I set AFCNTR in SPI_CFG2 (bit 31) "LL_SPI_EnableGPIOControl" in the LL library?

    Pavel A.
    Pavel A.Best answer
    January 22, 2024

    Yes exactly. Enable Master Keep IO state.

    oeliks
    oeliksAuthor
    Associate III
    January 22, 2024

    Thank You all for Your answers !

    oeliks
    oeliksAuthor
    Associate III
    January 23, 2024

    This setting solved the problem.

     

    IMG_2a.jpg