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UBart.2
UBart.2
Associate
March 26, 2023
Solved

Delayed interrupts during FMC access on stm32h7 ?

tested on nucleo stm32h723 board with STM32CubeIDE (only main.c is modified)

What does this example?

Timer3 triggers an interrupt every 40 microseconds. The interrupt toggles PC8 for ~2ms. Additionally we trigger a FMC data transfer every second for 10 seconds.

What is the Problem?

Every second during the FMC data transfer our interrupt handler is somehow delayed!

The global variable "ticks_end_max" contains the maximum number of the timer3 counter register just before the interrupt ends. This max counter value is ~2600, but only ~600 if FMC access commented out!

Using an oscilloscope on pins PC8 and PC9 is also possible. PC9 is configured as TIM3_CH4 and emits a 4us low pulse each cycle. PC8 is toggled for ~2us during interrupt. Trigger on rising edge of PC8 when PC9 is low.0693W00000aJiQAQA0.png

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waclawek.jan
waclawek.janBest answer
Super User
April 2, 2023

> It looks more like 5 or 6 transfers

There is probably some buffering at the AXI matrix output port towards FMC ("3 write acceptance" sounds much like a buffer for 3 writes). This is an independent mechanism from the processor's store buffer, and maybe you can influence it through the AXIM registers.

> 1) Is there any way to disable the 4-entry store buffer towards the AXI memory interface for a specific FMU region? Or to disabled it at all?

I don't think so.

> 2) Is there a way to flush the 4-entry store buffer or to check the fill status? I would not mind to just call a buffer flush after each single write to the slow IC.

Quoting from Cortex-M7 TRM:

The store buffer is drained of all stores to Strongly-ordered or Device memory before a load is

performed from Strongly-ordered or Device memory.

JW

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waclawek.jan
waclawek.jan
Super User
April 5, 2023

"Better" is heavily dependent on particular application's details here. For example, would the processor never access FMC (e.g. performing the FMC reads/writes exclusively through DMA), the processor's store buffer would not get clogged and GPIO write from processor would not get delayed. (Note that DMA would still clog the FMC row's buffer (probably 3-deep) in the AXI matrix, so if there are processor-originated accesses to FMC, even if to fast targets, the processor would need to wait until those accesses are fulfilled anyway).

It is most probably not be worth the hassle, though.

JW

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