Can two DMA work in parallel without competing for Bus?

[LLOLO.1]

Hi, I was wondering if the two DMA modules can work simultaneously without competing for Bus?

For example:

In BusMatrix.png file you can see that both DMA1 and DMA2 are connected SRAM1,SRAM2,AHB1 peripherals and AHB2 peripherals.

So if I set the DMA1 to get data from ADC1(In AHB2 Bus shown in Connections.png) to SRAM2 and set the DMA2 to get data from SRAM1 to USART1(In AHB1 Bus shown in Connections.png) are these two DMAs will compete to be the master of the bus? Or are they going to work simultaneously without disturbing each another?

If so, can this be used when there are no available bandwidth in DMA1 so ADC part can be moved to DMA2 to free up some bandwidth in DMA1?

[RMcCa]

Dunno, but the processor is using the same bus matrix, so i would guess that no, using more than one dma doesn't slow them down. I could be wrong, but i couldn't find any information about the speed of the dmas in a h745, so i decided not to worry about it and use as many dmas and mdmas as i need.​

[LLOLO.1]

I understand using more than one dma doesn't slow them down but will the performance increase when utilizing both DMAs with different memory location (SRAM1 and SRAM2) and different AHB busses?

[rromano001]

Hi, answer can be YES NO or DEPEND to.

If two DMA use same buses then Arbitration solve priority and usage.

If on different separated buses transfer run parallel.

If transfer is from two different BUS sharing one common source/destination then it depend on timing.

[LLOLO.1]

By saying "If on different separated buses transfer run parallel." you mean different Bus in Bus Matrix right? If different Slaves like SRAM1 and SRAM2 is used with DMA1 and DMA2 transfer is happening in parallel right?

[LLOLO.1]

So storing my ADC buffer in SRAM2 and USART1 buffer in SRAM1 and assigning different DMAs to control data transfers for these buffers will my DMAs work in parallel thus will increase the performance right (By performance I mean they won't collide with each other thus will have higher bandwidth)? Since ADC1 is in AHB2 and USART1 in AHB1 bus.

[RMcCa]

On some chips the 2 dmas work with different peripheral buses, but on chips with a dmamux the dma streams can be connected to any source. What speed are you running the adc and uart? If the speeds are slow compared to the processor i don't think it matters if the the dma accesses are simultaneous​ or sequential.

[LLOLO.1]

I know speed of ADC or UART is low compared to bus speeds and probably won't caused any problem when they are used with single DMA. I am not concerned with ADC or UART speed, I am just trying to understand this concept, significance of memory locations of buffers when using DMA and can DMAs used in parallel fashion when peripheral busses (AHB1, AHB2) and memory locations (SRAM1,SRAM2) are configured certain way and so on.

[LLOLO.1]

Also can DMA1 and DMA2 inside STM32G431KB access APB1 and APB2 simultaneously in parallel fashion?

[rromano001]

Hi, It is not simple answer this, I can answer about my IP CORE how use DMA and why I doubled bus access and parallelism on extreme bandwidth IE video generation/acquisition.

In your case ADC speed with USART too result in a fraction of CPU bandwidth.

Under these condition CPU is the primary bus winner and arbitration ratio (as from RMcCa answer) is not relevant to very few accesses.

In a large M2MDMA CPU lost arbitration cycle by cycle so it slow down. If involved memory area is video or network related, CPU is less important than animation effect or risk of network packet drop. These cases it is better raise DMA priority over CPU bus access.