We have STM32MP157c-DK2 board and we would like to run baremetal code on Cortex-A7 CPU1 while running Linux on Cortex-A7 CPU0.For that we need ROM code jump address for Cortex-A7 secondary CPU.If possible if you can give us the example or any documen

[CBakh.1209]

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[PatrickF]

As far as I know, ROM code does not start secondary CPU. ROM, TF-A and u-Boot only uses CPU0. CPU1 is started by the Kernel (I think this is not specific to OpenSTLinux).

Note that this kind of asymetric use case if likely not well supported by Cortex-A7. For example, inside Cortex-A7, the SMP bit must be set to 1 to enable data and L2 cache (so SMP=0 is not usable due to performance impact on DDR data accesses). Don't know if your bare-metal could run SMP=1 (common caches with coherency).

https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum/9921/l1-data-cache-and-unified-cache-disabled-in-amp-mode-for-cortex-a7

[CBakh.1209]

We want to start the secondary core from CPU0.As far as we read on ARM website,CPU0 is started initially and CPU1 is in WFI state.The primary core finishes the boot loader and immediately starts running Linux, while the secondary core waits in the boot loader for a jump address at particular memory location and CPU0 is responsible for writing the jump address at that particular memory location and sending the interrupt to CPU1.We need that particular memory location so that we can start the CPU1.

Link of ARM community where I got the above info.

https://community.arm.com/developer/ip-products/system/b/soc-design-blog/posts/smp-linux-on-a-minimal-dual-core-arm-cortex-a15-system

[PatrickF]

The jump location (and some other controls) is stored in backup registers, information is available here : https://wiki.st.com/stm32mpu/wiki/STM32MP15_backup_registers#At_boot_time