STM32MP257 & DP83869 fiber link

[tarzan2]

Hello,

I am using a STM32MP257 (Karo SOM), RGMII connected to a DP83869 (100Mbps fiber mode).

This is working well until I start the LVDS screen on my board.

• The screen is powered with 2 regulators : 
• Backlight (16V/360mA, dedicated boost)
• Logic (2.7V/500mA, dedicated buck)

The DP83869 is powered with 3 regulators :

• 1.1V (dedicated buck)
• 2.5V (dedicated LDO)
• 3.3V (shared buck also powering the MP2 SOM)

Below is the behavior in different configurations:

• Screen unplugged => fiber link OK
• Screen plugged => fiber link KO
  • hot-unplugging the screen makes the link working instantly
• Screen unplugged, flat cable present, with 100ohm R at the end of the LVDS signals => OK
• Screen unplugged, 
  • With no current on the BL / logic DC/DC converter => OK
  • Sinking 300mA on the BL => KO
    • Removing the sink current makes the link working instantly
  • Sinking 300mA on the logic => KO
    • Removing the sink current makes the link working instantly

Probing power rails with a scope show clean signals, in loaded and unloaded conditions.

The PHY clocks (CLOo, TX/RX CLK) are always clean 25MHz signals.

The feeling I have is that without screen, the link is "working by chance" and a slight noise emited by the screen regulators (when loaded) are making the link to fall. There is probably something wrong on the RGMII timings but I don't know how to check/set that.

Other points : 

*Where is hidden the GPIO slew rate data of STM32MP2? Nothing on datasheet, nothing in the user manual. Actually the device tree is configuring the MDC slew rate faster than the MDIO (<3> vs <0>).

* The DP83869 outputs a nIRQ line, requiring a 2.2k RPU (soldered). When the link is up and idle, this line is 0. When reading the MDIO IRQ registed, there is a pending IRQ ("link has changed").
** Reading the flag should clear the IRQ line but it is still stuck at 0
** The MP2 is configured with IRQ falling edge and should read the register, I shouldn't be able to read anything other than 0 in the IRQ register

Any help appreciated :)
Thanks

[tarzan2]

Some more informations :

• The screen is working :)
• The BL is dimable, and the link fall for all duty cycles excepted 0 (= no backight, boost converter in standby)

Below is the device tree of the fiber link:

 

&eth2 {
    pinctrl-names = "default", "sleep";
    pinctrl-0 = <&eth2_rgmii_pins_b>;
    pinctrl-1 = <&eth2_rgmii_sleep_pins_b>;
    phy-mode = "rgmii-id";
    max-speed = <100>;
    phy-handle = <&eth2_phy>;
    st,ext-phyclk;
    status = "okay";

    sfp0: sfp {
        compatible = "sff,sfp";
        i2c-bus = <&i2c6>;
        mod-def0-gpios = <&gpioh 10 GPIO_ACTIVE_LOW>;
        los-gpios = <&gpioe 1 GPIO_ACTIVE_LOW>;
        tx-fault-gpios = <&gpioe 3 GPIO_ACTIVE_LOW>;
        tx-disable-gpios = <&gpioe 2 GPIO_ACTIVE_HIGH>;
        rate-select0-gpios = <&gpioe 5 GPIO_ACTIVE_LOW>;
    };

    mdio {
        compatible = "snps,dwmac-mdio";
        #address-cells = <1>;
        #size-cells = <0>;

        eth2_phy: ethernet-phy@0 {
            /* compatible = "ethernet-phy-id2000.a0f3"; */
            reg = <0>;

            clocks = <&rcc CK_KER_ETH2>;
            interrupt-parent = <&gpiog>;
            interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
            reset-gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>;
            reset-assert-us = <50000>;
            reset-deassert-us = <500000>;
            ti,op-mode = <DP83869_RGMII_100_BASE>;
            max-speed = <100>;
            sfp = <&sfp0>;
            modif,quirk-disable-clk-125;
            modif,quirk-leds-cfg1 = <0xd230>;
            modif,quirk-gpio-mux-ctrl = <0x00ba>;
        };
        };
};

&pinctrl {
    eth2_rgmii_pins_b: eth2-rgmii-1 {
        pins1 {
            pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */
                 <STM32_PINMUX('C', 8, AF10)>, /* ETH_RGMII_TXD1 */
                 <STM32_PINMUX('C', 9, AF10)>, /* ETH_RGMII_TXD2 */
                 <STM32_PINMUX('C', 10, AF10)>, /* ETH_RGMII_TXD3 */
                 <STM32_PINMUX('C', 4, AF10)>; /* ETH_RGMII_TX_CTL */
            bias-disable;
            drive-push-pull;
            slew-rate = <3>;
            st,io-retime = <1>;
            st,io-clk-edge = <1>;
        };
        pins2 {
            pinmux = /* <STM32_PINMUX('H', 9, AF10)>, */ /* ETH_RGMII_CLK125 */
                 <STM32_PINMUX('F', 7, AF10)>, /* ETH_RGMII_GTX_CLK */
                 <STM32_PINMUX('G', 4, AF11)>; /* ETH_MDC */
            bias-disable;
            drive-push-pull;
            slew-rate = <3>;
        };
        pins3 {
            pinmux = <STM32_PINMUX('C', 5, AF10)>; /* ETH_MDIO */
            bias-disable;
            drive-push-pull;
            slew-rate = <0>;
        };
        pins4 {
            pinmux = <STM32_PINMUX('G', 0, AF10)>, /* ETH_RGMII_RXD0 */
                 <STM32_PINMUX('C', 12, AF10)>, /* ETH_RGMII_RXD1 */
                 <STM32_PINMUX('F', 9, AF10)>, /* ETH_RGMII_RXD2 */
                 <STM32_PINMUX('C', 11, AF10)>, /* ETH_RGMII_RXD3 */
                 <STM32_PINMUX('C', 3, AF10)>; /* ETH_RGMII_RX_CTL */
            bias-disable;
            st,io-retime = <1>;
            st,io-clk-edge = <1>;
        };
        pins5 {
            pinmux = <STM32_PINMUX('F', 6, AF10)>; /* ETH_RGMII_RX_CLK */
            bias-disable;
        };
    };

    eth2_rgmii_sleep_pins_b: eth2-rgmii-sleep-1 {
        pins {
            pinmux = <STM32_PINMUX('C', 7, ANALOG)>, /* ETH_RGMII_TXD0 */
                 <STM32_PINMUX('C', 8, ANALOG)>, /* ETH_RGMII_TXD1 */
                 <STM32_PINMUX('C', 9, ANALOG)>, /* ETH_RGMII_TXD2 */
                 <STM32_PINMUX('C', 10, ANALOG)>, /* ETH_RGMII_TXD3 */
                 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_TX_CTL */
                 /* <STM32_PINMUX('F', 8, ANALOG)>, */ /* ETH_RGMII_CLK125 */
                 <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_GTX_CLK */
                 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_MDC */
                 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_MDIO */
                 <STM32_PINMUX('G', 0, ANALOG)>, /* ETH_RGMII_RXD0 */
                 <STM32_PINMUX('C', 12, ANALOG)>, /* ETH_RGMII_RXD1 */
                 <STM32_PINMUX('F', 9, ANALOG)>, /* ETH_RGMII_RXD2 */
                 <STM32_PINMUX('C', 11, ANALOG)>, /* ETH_RGMII_RXD3 */
                 <STM32_PINMUX('C', 3, ANALOG)>, /* ETH_RGMII_RX_CTL */
                 <STM32_PINMUX('F', 6, ANALOG)>; /* ETH_RGMII_RX_CLK */
        };
    };
};

[PatrickF]

Hi,

boost and buck converter make a lot of current spikes at their inputs. Poor PCB routing like uncontrolled power/ground paths as well as decoupling could create a lot of troubles.
Did you carefully follow AN5489 for RGMII (including IO delays settings).
Maybe look to https://wiki.st.com/stm32mpu/wiki/How_to_tune_RGMII_GTX_clock_delay 

see also recommendation related to STPMIC25 as noise on VIN can also lead to issues on it’s supplies.
The STPMIC25 PCB layout guidelines

Regards.
 

[PatrickF]

See also this post as linked to Karo Sw delivery