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PatrickF
PatrickFBest answer
ST Employee
January 30, 2024

Hi @Roman Andronov 

The L2 is enabled together with L1 data cache.

See bit C in https://developer.arm.com/documentation/ddi0464/f/System-Control/Register-descriptions/System-Control-Register?lang=en

Obviously, need MMU correctly setup and SMP=1 (mandatory to have data cache) as well as I (for instruction cache).

Regards.

In order to give better visibility on the answered topics, please click on 'Best Answer' on the reply which solved your issue or answered your question.Tip of the day: Try Sidekick STM32 AI agent
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PatrickF
PatrickFBest answer
ST Employee
January 30, 2024

Hi @Roman Andronov 

The L2 is enabled together with L1 data cache.

See bit C in https://developer.arm.com/documentation/ddi0464/f/System-Control/Register-descriptions/System-Control-Register?lang=en

Obviously, need MMU correctly setup and SMP=1 (mandatory to have data cache) as well as I (for instruction cache).

Regards.

In order to give better visibility on the answered topics, please click on 'Best Answer' on the reply which solved your issue or answered your question.Tip of the day: Try Sidekick STM32 AI agent
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