STM32MP257FAK3 - Marvell 88E1512 IC probe error

[_Vanshika]

Hi,

I'm bringing up Ethernet (RGMII) on a custom STM32MP257 board using a Marvell 88E1512 PHY.

The MAC driver loads successfully, the PHY is detected, but bringing the interface up fails with a timeout.
I have attached the driver code, dts and pinctrl.dtsi for you reference.
 

eth1_mdio_pins_mx: eth1_mdio_mx-0 {

pins1 {

pinmux = <STM32_PINMUX('A', 9, AF10)>; /* ETH1_MDC */

bias-disable;

drive-push-pull;

slew-rate = <2>;

st,io-clk-edge = <0>;

st,io-retime = <0>;

st,io-delay-path = <0>;

st,io-delay = <0>;

};

pins2 {

pinmux = <STM32_PINMUX('A', 10, AF10)>; /* ETH1_MDIO */

bias-disable;

drive-push-pull;

slew-rate = <0>;

st,io-clk-edge = <0>;

st,io-retime = <0>;

st,io-delay-path = <0>;

st,io-delay = <0>;

};

};

eth1_mdio_sleep_pins_mx: eth1_mdio_sleep_mx-0 {

pins {

pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* ETH1_MDC */

<STM32_PINMUX('A', 10, ANALOG)>; /* ETH1_MDIO */

};

};

 

eth1_rgmii_pins_b: eth1-rgmii-1 {

pins1 {

pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */

<STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */

<STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */

<STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */

<STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */

bias-disable;

drive-push-pull;

slew-rate = <3>;

st,io-retime = <1>;

st,io-clk-edge = <1>;

};

pins2 {

pinmux = //<STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */

<STM32_PINMUX('C', 0, AF12)>; /* ETH_RGMII_GTX_CLK */

// <STM32_PINMUX('A', 9, AF10)>, /* ETH_MDC */

// <STM32_PINMUX('A', 10, AF10)>; /* ETH_MDIO */

bias-disable;

drive-push-pull;

slew-rate = <3>;

};

pins3 {

pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */

<STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */

<STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */

<STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */

<STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */

bias-disable;

st,io-retime = <1>;

st,io-clk-edge = <1>;

};

pins4 {

pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */

bias-disable;

};

};

 

eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 {

pins {

pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */

<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */

<STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */

<STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */

<STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */

//<STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */

<STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */

// <STM32_PINMUX('A', 9, ANALOG)>, /* ETH_MDC */

//<STM32_PINMUX('A', 10, ANALOG)>, /* ETH_MDIO */

<STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */

<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */

<STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */

<STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */

<STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */

<STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */

};

};

Kernel Log:
root@stm32mp25-discoc6-79-bf-52-95-cd:~# dmesg | grep eth
[    0.000000] psci: probing for conduit method from DT.
[    1.161022] optee: probing for conduit method.
[    8.639938] stm32-dwmac 482c0000.eth1: IRQ eth_lpi not found
[    8.660022] stm32-dwmac 482c0000.eth1: User ID: 0x1a, Synopsys ID: 0x53
[    8.671275] stm32-dwmac 482c0000.eth1:     DWMAC4/5
[    8.683834] stm32-dwmac 482c0000.eth1: DMA HW capability register supported
[    8.690657] stm32-dwmac 482c0000.eth1: RX Checksum Offload Engine supported
[    8.697664] stm32-dwmac 482c0000.eth1: TX Checksum insertion supported
[    8.704145] stm32-dwmac 482c0000.eth1: Wake-Up On Lan supported
[    8.704235] stm32-dwmac 482c0000.eth1: TSO supported
[    8.720125] stm32-dwmac 482c0000.eth1: Enable RX Mitigation via HW Watchdog Timer
[    8.727694] stm32-dwmac 482c0000.eth1: device MAC address 2e:a8:77:43:1e:cc
[    8.735033] stm32-dwmac 482c0000.eth1: Enabled L3L4 Flow TC (entries=2)
[    8.750276] stm32-dwmac 482c0000.eth1: Enabled RFS Flow TC (entries=10)
[    8.764772] stm32-dwmac 482c0000.eth1: TSO feature enabled
[    8.770256] stm32-dwmac 482c0000.eth1: Using 32/32 bits DMA host/device width
[    9.651311] stm32-dwmac 482c0000.eth1 end0: renamed from eth0
[   10.092728] Modules linked in: usb_f_ncm u_ether libcomposite ar0521 ili210x crc_ccitt pwm_stm32 crct10dif_ce phy_stm32_usb2phy marvell rtc_stm32 dwmac_stm32 mr75203 hci_uart btqca stmmac_platform pcie_stm32(+) btbcm hantro_vpu stmmac galcore(O) stm32_dcmipp stm32_csi pcs_xpcs v4l2_jpeg v4l2_vp9 v4l2_h264 v4l2_mem2mem bluetooth v4l2_fwnode videobuf2_dma_contig videobuf2_vmalloc videobuf2_memops phy_stm32_combophy videobuf2_v4l2 v4l2_async videodev lvds ecdh_generic videobuf2_common ecc rfkill dwc3_stm32 mc stm32_lptimer usbh_stm32 stm32_cryp crypto_engine stm32_crc32 libdes i2c_stm32f7_drv i2c_smbus stm32_timers snd_soc_stm32_i2s stm32_rproc rotary_encoder panel_lvds stm32_m0_rproc pwm_bl display_connector mailbox_client_cdev snd_soc_dmic sch_fq_codel nfnetlink ip_tables x_tables ipv6
[   10.393993] Modules linked in: usb_f_ncm u_ether libcomposite ar0521 ili210x crc_ccitt pwm_stm32 crct10dif_ce phy_stm32_usb2phy marvell rtc_stm32 dwmac_stm32 mr75203 hci_uart btqca stmmac_platform pcie_stm32 btbcm hantro_vpu stmmac galcore(O) stm32_dcmipp stm32_csi pcs_xpcs v4l2_jpeg v4l2_vp9 v4l2_h264 v4l2_mem2mem bluetooth v4l2_fwnode videobuf2_dma_contig videobuf2_vmalloc videobuf2_memops phy_stm32_combophy videobuf2_v4l2 v4l2_async videodev lvds ecdh_generic videobuf2_common ecc rfkill dwc3_stm32 mc stm32_lptimer usbh_stm32 stm32_cryp crypto_engine stm32_crc32 libdes i2c_stm32f7_drv i2c_smbus stm32_timers snd_soc_stm32_i2s stm32_rproc rotary_encoder panel_lvds stm32_m0_rproc pwm_bl display_connector mailbox_client_cdev snd_soc_dmic sch_fq_codel nfnetlink ip_tables x_tables ipv6
[   12.857054] stm32-dwmac 482c0000.eth1 end0: Register MEM_TYPE_PAGE_POOL RxQ-0
[   12.860244] stm32-dwmac 482c0000.eth1 end0: Register MEM_TYPE_PAGE_POOL RxQ-1
[   13.765486] stm32-dwmac 482c0000.eth1 end0: __stmmac_open: Cannot attach to PHY (error: -110)

root@stm32mp25-discoc6-79-bf-52-95-cd:~# dmesg | grep eth0
[    9.651311] stm32-dwmac 482c0000.eth1 end0: renamed from eth0

root@stm32mp25-discoc6-79-bf-52-95-cd:~# dmesg | grep end0
[    9.651311] stm32-dwmac 482c0000.eth1 end0: renamed from eth0
[   12.857054] stm32-dwmac 482c0000.eth1 end0: Register MEM_TYPE_PAGE_POOL RxQ-0
[   12.860244] stm32-dwmac 482c0000.eth1 end0: Register MEM_TYPE_PAGE_POOL RxQ-1
[   13.765486] stm32-dwmac 482c0000.eth1 end0: __stmmac_open: Cannot attach to PHY (error: -110)

root@stm32mp25-discoc6-79-bf-52-95-cd:~# dmesg | grep mac
[    8.639938] stm32-dwmac 482c0000.eth1: IRQ eth_lpi not found
[    8.660022] stm32-dwmac 482c0000.eth1: User ID: 0x1a, Synopsys ID: 0x53
[    8.671275] stm32-dwmac 482c0000.eth1:     DWMAC4/5
[    8.683834] stm32-dwmac 482c0000.eth1: DMA HW capability register supported
[    8.690657] stm32-dwmac 482c0000.eth1: RX Checksum Offload Engine supported
[    8.697664] stm32-dwmac 482c0000.eth1: TX Checksum insertion supported
[    8.704145] stm32-dwmac 482c0000.eth1: Wake-Up On Lan supported
[    8.704235] stm32-dwmac 482c0000.eth1: TSO supported
[    8.720125] stm32-dwmac 482c0000.eth1: Enable RX Mitigation via HW Watchdog Timer
[    8.727694] stm32-dwmac 482c0000.eth1: device MAC address 2e:a8:77:43:1e:cc
[    8.735033] stm32-dwmac 482c0000.eth1: Enabled L3L4 Flow TC (entries=2)
[    8.750276] stm32-dwmac 482c0000.eth1: Enabled RFS Flow TC (entries=10)
[    8.764772] stm32-dwmac 482c0000.eth1: TSO feature enabled
[    8.770256] stm32-dwmac 482c0000.eth1: Using 32/32 bits DMA host/device width
[    9.651311] stm32-dwmac 482c0000.eth1 end0: renamed from eth0
[   10.092728] Modules linked in: usb_f_ncm u_ether libcomposite ar0521 ili210x crc_ccitt pwm_stm32 crct10dif_ce phy_stm32_usb2phy marvell rtc_stm32 dwmac_stm32 mr75203 hci_uart btqca stmmac_platform pcie_stm32(+) btbcm hantro_vpu stmmac galcore(O) stm32_dcmipp stm32_csi pcs_xpcs v4l2_jpeg v4l2_vp9 v4l2_h264 v4l2_mem2mem bluetooth v4l2_fwnode videobuf2_dma_contig videobuf2_vmalloc videobuf2_memops phy_stm32_combophy videobuf2_v4l2 v4l2_async videodev lvds ecdh_generic videobuf2_common ecc rfkill dwc3_stm32 mc stm32_lptimer usbh_stm32 stm32_cryp crypto_engine stm32_crc32 libdes i2c_stm32f7_drv i2c_smbus stm32_timers snd_soc_stm32_i2s stm32_rproc rotary_encoder panel_lvds stm32_m0_rproc pwm_bl display_connector mailbox_client_cdev snd_soc_dmic sch_fq_codel nfnetlink ip_tables x_tables ipv6
[   10.393993] Modules linked in: usb_f_ncm u_ether libcomposite ar0521 ili210x crc_ccitt pwm_stm32 crct10dif_ce phy_stm32_usb2phy marvell rtc_stm32 dwmac_stm32 mr75203 hci_uart btqca stmmac_platform pcie_stm32 btbcm hantro_vpu stmmac galcore(O) stm32_dcmipp stm32_csi pcs_xpcs v4l2_jpeg v4l2_vp9 v4l2_h264 v4l2_mem2mem bluetooth v4l2_fwnode videobuf2_dma_contig videobuf2_vmalloc videobuf2_memops phy_stm32_combophy videobuf2_v4l2 v4l2_async videodev lvds ecdh_generic videobuf2_common ecc rfkill dwc3_stm32 mc stm32_lptimer usbh_stm32 stm32_cryp crypto_engine stm32_crc32 libdes i2c_stm32f7_drv i2c_smbus stm32_timers snd_soc_stm32_i2s stm32_rproc rotary_encoder panel_lvds stm32_m0_rproc pwm_bl display_connector mailbox_client_cdev snd_soc_dmic sch_fq_codel nfnetlink ip_tables x_tables ipv6
[   12.857054] stm32-dwmac 482c0000.eth1 end0: Register MEM_TYPE_PAGE_POOL RxQ-0
[   12.860244] stm32-dwmac 482c0000.eth1 end0: Register MEM_TYPE_PAGE_POOL RxQ-1
[   12.957454] Marvell 88E1510 stmmac-0:01: phydev->mdio.addr = 1
[   12.957716] Marvell 88E1510 stmmac-0:01: phydev->phy_id = 0x01410dd0
[   12.972255] Marvell 88E1510 stmmac-0:01: ========== m88e1510_config_init ==========
[   12.977452] Marvell 88E1510 stmmac-0:01: Initial BMCR = 0xffff
[   12.980425] Marvell 88E1510 stmmac-0:01: PHY ID1 = 0xffff
[   12.987506] Marvell 88E1510 stmmac-0:01: PHY ID2 = 0xffff
[   12.991086] Marvell 88E1510 stmmac-0:01: phy_interface = 10
[   12.997427] Marvell 88E1510 stmmac-0:01: Switched to page 0x00FF
[   13.002693] Marvell 88E1510 stmmac-0:01: Errata[0]: reg17=0x214b reg16=0x2144
[   13.013604] Marvell 88E1510 stmmac-0:01: Errata[1]: reg17=0x0c28 reg16=0x2146
[   13.018090] Marvell 88E1510 stmmac-0:01: Errata[2]: reg17=0xb233 reg16=0x214d
[   13.036156] Marvell 88E1510 stmmac-0:01: Errata[3]: reg17=0xcc0c reg16=0x2159
[   13.057709] Marvell 88E1510 stmmac-0:01: Switched to page 0x00FB
[   13.058162] Marvell 88E1510 stmmac-0:01: Writing reg7 = 0xC00D
[   13.077450] Marvell 88E1510 stmmac-0:01: Returned to Copper page
[   13.077913] Marvell 88E1510 stmmac-0:01: RGMII interface detected, skipping SGMII configuration
[   13.097416] Marvell 88E1510 stmmac-0:01: Calling m88e1011_set_downshift()
[   13.737936] Marvell 88E1510 stmmac-0:01: phy_poll_reset failed: -110
[   13.738710] Marvell 88E1510 stmmac-0:01: Downshift failed (-110)
[   13.765486] stm32-dwmac 482c0000.eth1 end0: __stmmac_open: Cannot attach to PHY (error: -110)

What is the reason for this error. How can this error be resolved.
Reset and clock are coming when checked using oscilloscope.

[Jhonwickson]

 

From the logs, the PHY is initially detected, but later all PHY registers read 0xFFFF and phy_poll_reset failed (-110) indicates the PHY is no longer responding over MDIO.

A few things I'd verify first:

• Double-check the PHY reset timing against the 88E1512 datasheet (hold/reset delays after power-up).
• Confirm the RGMII clock mode (internal PHY delay vs. MAC delay) and DTS phy-mode match your hardware.
• Verify MDIO/MDC signal integrity during the failure (not just reset/clock) and ensure the PHY power rails remain stable.
• Compare your DTS and pinctrl with the STM32MP257 Ethernet reference design to rule out pinmux or clock configuration issues.

Since the PHY ID changes to 0xFFFF, this looks more like a hardware, reset, or MDIO communication issue than a MAC driver problem.

[_Vanshika]

Hi,

I verified the hardware signals using an oscilloscope:

• The PHY reset sequence is correct and follows the timing requirements.

• MDC and MDIO signals are present and look normal.

• The reference clocks are also present and stable.

• The PHY power rails remain stable during boot.

I also noticed that the Marvell driver (marvell.c) is successfully matched with the PHY and m88e1510_config_init() is called. The kernel detects the PHY with ID 0x01410dd0, but once the configuration starts, subsequent MDIO reads return 0xFFFF, and phy_poll_reset() times out with -110.

My PHY device is Marvell 88E1512, while the driver appears to use the 88E1510 configuration path.
Is there any additional patch or specific support required for the 88E1512 on the STM32MP257 platform? Is there a recommended driver update or patch that should be applied?

Any guidance would be appreciated.