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asadullah4571
asadullah4571
Associate III
June 26, 2026
Solved

Clarification Required: DRAM Block B Necessity with Micron MT53E1G32D2FW 4GB LPDDR4 on STM32MP257

  • June 26, 2026
  • 4 replies
  • 80 views

Dear Team,

I hope this email finds you well.

 

I am writing to seek your expert clarification on a critical hardware design decision we are currently evaluating for our STM32MP257-based custom board.

 

 

 

--- Current Memory Configuration ---

 

• SoC         : STM32MP257

• Memory Part : Micron MT53E1G32D2FW-046 WT:C

• Type        : LPDDR4

• Density     : 32 Gbit (4 GB)

• Organization: 1 x32 (Dual Channel — Channel A + Channel B)

 

--- Our Understanding from ST Documentation ---

 

Based on our research of the following official ST documents:

 

1. AN5723 (Rev 3, Aug 2024) :

   "Interface width is 32-bit when full-populated, or 16-bit when half-populated."

 

2. AN5724 — DDR Routing Guide:

   "For the 16-bit LPDDR4 interface, one 16-bit LPDDR4 is used in point-to-point connection. With this configuration it can drive up to 2 Gbyte memory."

 

3. AN5489 (Rev 6, Sep 2025) :

   STM32MP257 supports both 16-bit (half-populated) and 32-bit (full-populated) LPDDR4 configurations.

 

Our understanding is:

• If using a native x16 LPDDR4 device → DRAM_B is NOT required (half-populated, 2 GB)

• If using our current 1x32 device (Micron MT53E1G32D2FW) → DRAM_B IS required (full-populated, 4 GB), since it is a dual-channel x32 device that needs both Channel A and Channel B connected simultaneously

 

--- Clarification Requested ---

 

Could you kindly confirm or correct the following:

 

1. With our current Micron MT53E1G32D2FW (x32, 4 GB) device, is it safe and supported to leave DRAM_B  unconnected?

 

2. If DRAM_B can be left unconnected with this x32 device, would the DDR PHY training still pass successfully at boot?

 

3. If DRAM_B must be connected for this specific device, would switching to a x16 LPDDR4 device (e.g., Micron MT53E1G16D2FW) be the correct approach to eliminate DRAM_B routing?

 

This clarification is critical for us before we proceed with PCB routing, as it directly impacts our layer stack-up, routing complexity, and BOM decisions.

 

Thank you very much for your time and guidance. We look forward to your expert advice.

Best answer by ZAKARIA_C1

Hello ​@asadullah4571,

 

The test was performed using the MP25-DK board (MB1605) as the reference platform, with a 4 GB, 32-bit LPDDR4 running at 1.2 GHz.

We created a new configuration by changing only the bus width to 16 bits and the total memory size to 2 GB.

In the settings file, this results in the following changes:

-#define DDR_MEM_NAME  "LPDDR4 1x32Gbits 1x32bits 1200MHz"
+#define DDR_MEM_NAME  "LPDDR4 1x32Gbits 1x16bits 1200MHz"
-#define DDR_MEM_SIZE  0x100000000UL
+#define DDR_MEM_SIZE  0x80000000UL
-#define DDR_MSTR 0x01080020U
+#define DDR_MSTR 0x01081020U
-#define DDR_ADDRMAP1 0x00080808U
+#define DDR_ADDRMAP1 0x00070707U
-#define DDR_ADDRMAP3 0x00000000U
+#define DDR_ADDRMAP3 0x1F000000U
-#define DDR_ADDRMAP5 0x070F0707U
+#define DDR_ADDRMAP5 0x060F0606U
-#define DDR_ADDRMAP6 0x07070707U
+#define DDR_ADDRMAP6 0x06060606U
-#define DDR_ADDRMAP7 0x00000F07U
+#define DDR_ADDRMAP7 0x00000F06U
-#define DDR_ADDRMAP9 0x07070707U
+#define DDR_ADDRMAP9 0x06060606U
-#define DDR_ADDRMAP10 0x07070707U
+#define DDR_ADDRMAP10 0x06060606U
-#define DDR_ADDRMAP11 0x00000007U
+#define DDR_ADDRMAP11 0x00000006U
-#define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000002
+#define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000000
With these changes, we are able to boot successfully and pass the tests without any issues.

PS : In the test setup, the DRAM_B signals remained connected, and there is therefore a high chance that this would fail during DDR PHY training in your case, because the training is still performed on all four DBYTEs (32 bits), while in the end only two of them (16 bits) are actually used.

Best Regards,
Zakaria

4 replies

W
Windows
Associate II
June 30, 2026

Hi ​@asadullah4571 

Why use MT53E1G32D2FW-046 WT:C?

They are out of stock at the moment.

 

By the way! I purchased a MT53E1G32D2FW-046 WT:C from Aliexpress, but I could only use 2 GB. It's working very well.

Z
ZAKARIA_C1
ST Employee
July 3, 2026

Hello ​@asadullah4571,

A test is currently being prepared to verify this.
If everything is okay, I will post a reply to keep you informed, but in the meantime No, we cannot guarantee that it will work properly at the moment.
The same applies to the second question: we are not sure it will pass the DDR PHY training either.

Therefore, the best option is to use a 16-bit LPDDR4 and leave the MPU balls for the upper 16-bit part unconnected.

Best Regards,
Zakaria

In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question.
    Z
    ZAKARIA_C1Best answer
    ST Employee
    July 3, 2026

    Hello ​@asadullah4571,

     

    The test was performed using the MP25-DK board (MB1605) as the reference platform, with a 4 GB, 32-bit LPDDR4 running at 1.2 GHz.

    We created a new configuration by changing only the bus width to 16 bits and the total memory size to 2 GB.

    In the settings file, this results in the following changes:

    -#define DDR_MEM_NAME  "LPDDR4 1x32Gbits 1x32bits 1200MHz"
    +#define DDR_MEM_NAME  "LPDDR4 1x32Gbits 1x16bits 1200MHz"
    -#define DDR_MEM_SIZE  0x100000000UL
    +#define DDR_MEM_SIZE  0x80000000UL
    -#define DDR_MSTR 0x01080020U
    +#define DDR_MSTR 0x01081020U
    -#define DDR_ADDRMAP1 0x00080808U
    +#define DDR_ADDRMAP1 0x00070707U
    -#define DDR_ADDRMAP3 0x00000000U
    +#define DDR_ADDRMAP3 0x1F000000U
    -#define DDR_ADDRMAP5 0x070F0707U
    +#define DDR_ADDRMAP5 0x060F0606U
    -#define DDR_ADDRMAP6 0x07070707U
    +#define DDR_ADDRMAP6 0x06060606U
    -#define DDR_ADDRMAP7 0x00000F07U
    +#define DDR_ADDRMAP7 0x00000F06U
    -#define DDR_ADDRMAP9 0x07070707U
    +#define DDR_ADDRMAP9 0x06060606U
    -#define DDR_ADDRMAP10 0x07070707U
    +#define DDR_ADDRMAP10 0x06060606U
    -#define DDR_ADDRMAP11 0x00000007U
    +#define DDR_ADDRMAP11 0x00000006U
    -#define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000002
    +#define DDR_UIB_NUMACTIVEDBYTEDFI1 0x00000000
    With these changes, we are able to boot successfully and pass the tests without any issues.

    PS : In the test setup, the DRAM_B signals remained connected, and there is therefore a high chance that this would fail during DDR PHY training in your case, because the training is still performed on all four DBYTEs (32 bits), while in the end only two of them (16 bits) are actually used.

    Best Regards,
    Zakaria

    In order to give better visibility on the answered topics, please click on 'Best answer' on the reply which solved your issue or answered your question.
      asadullah4571
      asadullah4571Author
      Associate III
      July 10, 2026

      ​@ZAKARIA_C1 

      Thanks for the quick Response

      I Think It should Work From my side I will try to disconnect the Balls , and then again we should try. As of now it is Production Stage , One’s the hardware revision will change Will try with the same 
       

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