FAQ: How to setup the SDMMC_CK clock frequency in Linux
In the sdmmc information command below, the timing specification is mmc DDR52, whereas the clock frequency on the SDMMC_CK pin is only 12.5 MHz. Why?
This article also applies to the STM32MP2 series. The principle for adjusting the clock is independent of the SoC hardware.
root@stm32mp151c-oeswa63:~# cat /sys/kernel/debug/mmc0/ios
clock: 25000000 Hz <<<<<« SDMMC kernel clock
actual clock: 12500000 Hz <<<<< Clock frequency on the SDMMC_CK pin selected by the driver
vdd: 21 (3.3 to 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (do not care)
power mode: 2 (on)
bus width: 3 (8 bits)
timing spec: 8 (MMC DDR52)
signal voltage: 0 (3.30 V)
driver type: 0 (driver type B)
The Linux SDMMC driver selects the highest possible frequency for the SDMMC_CK pin within the maximum frequency defined by the SDMMC mode in the device tree binding file and the table below.
The frequency on the SDMMC_CK pin depends on the SDMMC kernel clock and the SDMMC divider. The minimum divider is 2 when SDMMC is in DDR mode and 1 when SDMMC is in SDR mode (RM0436 rev 5, figure 693).
RCC setup
PLL4P settings in TF-A device tree:
cfg = < 1 42 20 7 7 PQR(1,0,1) >;
frac = < 0x1800 >;
Let's decode the PLL settings from this two device tree lines,
Clock device tree configuration - stm32mpu
HSE=24 Mhz
PLL4 freq= HSE/2 * (42+1 + 0x1800/8192) = 12 * 43.75 = 525 MHz
20=>DIVP=21 ->525/21=25 MHz
0x1800 = 6144
8192 value from RefMan FRACV definition
FracN provide decimal value, between 0 min and almost 1 (8191/8192))
So in current situation, PLL4P is 25 MHz.
and selects the highest clock below 52 MHz freq with div=2. It sets SDMMC_CK to PLL4P/2 =12.5 MHz.
The RCC setup of the previous command is as follows. SDMMC is connected to eMMC in DDR mode, eMMC HighSpeed (see the table below), with the SDMMC kernel clock source set to PLL4P.
PLL4P settings in the TF-A device tree:
cfg = < 1 42 20 7 7 PQR(1,0,1) >; frac = < 0x1800 >;
The following text decodes the PLL settings from these two device tree lines.
Clock device tree configuration - stm32mpu
HSE = 24 MHz.
PLL4 frequency = HSE / 2 × (42 + 1 + 0x1800 / 8192) = 12 × 43.75 = 525 MHz.
20 => DIVP = 21 -> 525 / 21 = 25 MHz.
0x1800 = 6144.
The value 8192 comes from the reference manual definition of FRACV.
FRACN provides a decimal value between 0 and almost 1 (8191 / 8192).
In the current situation, PLL4P is 25 MHz.
The driver sets DDR mode to eMMC HighSpeed (mmc-ddr-3_3v is in the SDMMC device tree node) and selects the highest clock below 52 MHz with div = 2.
It sets SDMMC_CK to PLL4P / 2 = 12.5 MHz.
PLL frequency for the SDMMC kernel clock
Assume that PLL3R (104.5 MHz) is intended for SDMMC and that PLL4P (89.57 MHz) is intended for Ethernet. Using PLL3R at 104.5 MHz for SDMMC is less suitable than using PLL4P at 89.57 MHz.
In the device tree, the SDMMC mode is mmc-ddr-3_3v (see the binding and the tables below). The maximum SDMMC_CK is 52 MHz.
It is better to set PLL4P to 89.57 MHz so that SDMMC_CK is 44.785 MHz.
If 104.5 MHz / 2 = 52.25 MHz, which is greater than 52 MHz, the driver does not use div = 2. It uses div = 4, so 104.5 MHz / 4 = 26.125 MHz.
The possible parent clocks for the SDMMC kernel clock are listed here: https://github.com/STMicroelectronics/u-boot/blob/v2020.10-stm32mp/include/dt-bindings/clock/stm32mp1-clksrc.h
The device tree property st,pkcs selects the parent clock. For STM32MP2, the device tree property st,flexgen selects the parent clock.
Clock device tree configuration for stm32mpu
Background information
The SMMDC mode is set according to the flash device and the expected speed. Not all modes are supported by hardware. For example, HS400 is not supported on eMMC.
The driver modes are defined in the device tree file linux/Documentation/devicetree/bindings/mmc/mmc-controller.yaml in v6.6-stm32mp of STMicroelectronics/linux.
The maximum frequency of SDMMC_CK is given in the tables of RM0436 Rev 7, SDMMC operation modes. This value is a maximum. For example, in "eMMC High speed DDR" mode, SDMMC_CK can use any frequency from 0 to 52 MHz.
In STM32MP1 RefMan0436, the tables indicate that HS200 supports a maximum clock of 200 MHz, as defined in the JEDEC standard.
But on STM32MP1, the maximum SDMMC_CK frequency for eMMC and SD card is 100 MHz, not 130 MHz.
The I/O maximum speed is the limiting factor.